Visible to Intel only — GUID: bhc1410937278059
Ixiasoft
1. SDI II Intel® FPGA IP Quick Reference
2. SDI II IP Core Overview
3. SDI II IP Core Getting Started
4. SDI II IP Core Parameters
5. SDI II IP Core Functional Description
6. SDI II IP Core Signals
7. SDI II IP Core Design Considerations
8. SDI II IP Core Testbench and Design Examples
9. SDI II Intel® FPGA IP User Guide Archives
10. Document Revision History for the SDI II Intel® FPGA IP User Guide
5.3.1. Insert Line
5.3.2. Insert/Check CRC
5.3.3. Insert Payload ID
5.3.4. Match TRS
5.3.5. Scrambler
5.3.6. TX Sample
5.3.7. Clock Enable Generator
5.3.8. RX Sample
5.3.9. Detect Video Standard
5.3.10. Detect 1 and 1/1.001 Rates
5.3.11. Transceiver Controller
5.3.12. Descrambler
5.3.13. TRS Aligner
5.3.14. 3Gb Demux
5.3.15. Extract Line
5.3.16. Extract Payload ID
5.3.17. Detect Format
5.3.18. Sync Streams
5.3.19. Convert SD Bits
5.3.20. Insert Sync Bits
5.3.21. Remove Sync Bits
5.4.1. HD-SDI Dual Link to 3G-SDI (Level B) Conversion
5.4.2. 3G-SDI (Level B) to HD-SDI Dual Link Conversion
5.4.3. SMPTE RP168 Switching Support
5.4.4. SD 20-Bit Interface for Dual/Triple Rate
5.4.5. Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices
5.4.6. Intel FPGA Video Streaming Interface
7.1.2.1. Changing RX CDR Reference Clock in Transceiver Native PHY IP Core
7.1.2.2. Merging Simplex Mode Transceiver in the Same Channel
7.1.2.3. Using Generated Reconfiguration Management for Triple and Multi Rates
7.1.2.4. Ensuring Independent RX and TX Operations in the Same Channel
7.1.2.5. Potential Routing Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
7.1.2.6. Unconstrained Clocks in SDI Multi-Rate RX Using Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
7.1.2.7. Unused Transceiver Channels
7.1.2.8. Routing Transceiver Reference Clock Pins to Core Logic in Intel® Stratix® 10 Devices
Visible to Intel only — GUID: bhc1410937278059
Ixiasoft
7.1.1.1. Modifying the Transceiver Reconfiguration Controller
Perform the following changes to modify the transceiver reconfiguration controller:
- Edit the Number_of_reconfig_interfaces parameter. This parameter specifies the total number of reconfiguration interfaces that connect to this block.
- Each channel or TX PLL needs one reconfiguration interface. Therefore, an SDI duplex or SDI TX mode requires two interfaces while an SDI RX mode requires only one interface. If you enable the dynamic TX clock switching feature, the SDI duplex or SDI TX mode requires three interfaces. The additional interface is for the additional TX PLL. For simplicity, assume this option is disabled.
- Determine the total number of reconfiguration interfaces required in your design and assign the parameter value accordingly. In this design example, the total number of reconfiguration interfaces is 7 (Ch0=2, Ch1=3 and Ch2=2).
- Link the reconfig_to_xcvr and reconfig_from_xcvr signals from the additional SDI duplex instance at Ch2. You must link the signals in the order of the logical channel number (rx_log_ch_num and tx_log_ch_num) in the reconfiguration logic source file (sdi_ii_reconfig_logic.v).
- In the design example that instantiates the transceiver reconfiguration controller, add the wire connection between the additional SDI duplex instance at Ch2 and the transceiver reconfiguration controller as shown below:
wire [ 139:0] reconfig_to_xcvr_du_ch2; wire [ 91:0] reconfig_from_xcvr_du_ch2; wire [ 139:0] reconfig_to_xcvr_tx_ch1; wire [ 69:0] reconfig_to_xcvr_rx_ch1; wire [ 91:0] reconfig_from_xcvr_tx_ch1; wire [ 45:0] reconfig_from_xcvr_rx_ch1; wire [ 139:0] reconfig_to_xcvr_du_ch0; wire [ 91:0] reconfig_from_xcvr_du_ch0; alt_xcvr_reconfig #( .number_of_reconfig_interfaces (7), …. ) u_reconfig ( .reconfig_to_xcvr ({reconfig_to_xcvr_du_ch2, reconfig_to_xcvr_tx_ch1, reconfig_to_xcvr_rx_ch1, reconfig_to_xcvr_du_ch0}), .reconfig_from_xcvr ({reconfig_from_xcvr_du_ch2, reconfig_from_xcvr_tx_ch1, reconfig_from_xcvr_rx_ch1, reconfig_from_xcvr_du_ch0}), );