SDI II Intel® FPGA IP User Guide

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ID 683133
Date 10/05/2023
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Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Quick Reference 2. SDI II IP Core Overview 3. SDI II IP Core Getting Started 4. SDI II IP Core Parameters 5. SDI II IP Core Functional Description 6. SDI II IP Core Signals 7. SDI II IP Core Design Considerations 8. SDI II IP Core Testbench and Design Examples 9. SDI II Intel® FPGA IP User Guide Archives 10. Document Revision History for the SDI II Intel® FPGA IP User Guide
2. SDI II IP Core Overview x
2.1. Release Information 2.2. Device Family Support 2.3. General Description 2.4. Performance and Resource Utilization
3. SDI II IP Core Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Design Walkthrough 3.3. SDI II IP Core Component Files 3.4. Compiling the SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.2. Design Walkthrough x
3.2.1. Creating a New Intel® Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. SDI II IP Core Functional Description x
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol x
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules x
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features x
5.4.1. HD-SDI Dual Link to 3G-SDI (Level B) Conversion 5.4.2. 3G-SDI (Level B) to HD-SDI Dual Link Conversion 5.4.3. SMPTE RP168 Switching Support 5.4.4. SD 20-Bit Interface for Dual/Triple Rate 5.4.5. Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices 5.4.6. Intel FPGA Video Streaming Interface
5.4.6. Intel FPGA Video Streaming Interface x
5.4.6.1. RGB Pixel Packing 5.4.6.2. YCbCr 444 Pixel Packing 5.4.6.3. YCbCr 422 Pixel Packing 5.4.6.4. Supported Modes
6. SDI II IP Core Signals x
6.1. SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals 6.5. Transmitter Streaming Video and Control Signals 6.6. Receiver Streaming Video and Control Signals
6.2. Transmitter Protocol Signals x
6.2.1. Image Mapping
6.3. Receiver Protocol Signals x
6.3.1. rx_format
7. SDI II IP Core Design Considerations x
7.1. Transceiver Handling Guidelines 7.2. Timing Violation 7.3. SDI II IP Core Registers
7.1. Transceiver Handling Guidelines x
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices 7.1.2. Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices 7.1.3. Handling Transceiver in Intel Agilex® 7 F-Tile Devices
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices x
7.1.1.1. Modifying the Transceiver Reconfiguration Controller 7.1.1.2. Modifying the Reconfiguration Management 7.1.1.3. Modifying the Reconfiguration Router
7.1.2. Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices x
7.1.2.1. Changing RX CDR Reference Clock in Transceiver Native PHY IP Core 7.1.2.2. Merging Simplex Mode Transceiver in the Same Channel 7.1.2.3. Using Generated Reconfiguration Management for Triple and Multi Rates 7.1.2.4. Ensuring Independent RX and TX Operations in the Same Channel 7.1.2.5. Potential Routing Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 7.1.2.6. Unconstrained Clocks in SDI Multi-Rate RX Using Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 7.1.2.7. Unused Transceiver Channels 7.1.2.8. Routing Transceiver Reference Clock Pins to Core Logic in Intel® Stratix® 10 Devices
7.1.3. Handling Transceiver in Intel Agilex® 7 F-Tile Devices x
7.1.3.1. System PLL Clocking Mode 7.1.3.2. RX Transceiver Settings 7.1.3.3. TX Transceiver Settings 7.1.3.4. Unused Transceiver Tiles 7.1.3.5. Dynamic Reconfiguration 7.1.3.6. SD-SDI Timing Jitter With External VCXO Which Receive FVH Sync Signals
7.1.3.2. RX Transceiver Settings x
7.1.3.2.1. Multi-rate Designs 7.1.3.2.2. Triple-rate Designs 7.1.3.2.3. Single-rate Designs
7.3. SDI II IP Core Registers x
7.3.1. SDI II Tx Register Summary 7.3.2. SDI II Tx Register Description 7.3.3. SDI II Rx Register Summary 7.3.4. SDI II Rx Register Description
8. SDI II IP Core Testbench and Design Examples x
8.1. Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile Devices 8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices
8.1. Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile Devices x
8.1.1. Design Example Presets
8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices x
8.2.1. Design Example Components 8.2.2. Design Reference 8.2.3. Simulating the SDI II IP Core Design
8.2.1. Design Example Components x
8.2.1.1. Video Pattern Generator 8.2.1.2. Transceiver Reconfiguration Controller 8.2.1.3. Reconfiguration Management 8.2.1.4. Reconfiguration Router 8.2.1.5. Avalon® Memory-Mapped Interface Translators
8.2.2. Design Reference x
8.2.2.1. Video Pattern Generator Signals 8.2.2.2. Transceiver Reconfiguration Controller Signals 8.2.2.3. Reconfiguration Management Parameters 8.2.2.4. Reconfiguration Router Signals
8.2.3. Simulating the SDI II IP Core Design x
8.2.3.1. Simulation Run Time
1. SDI II Intel® FPGA IP Quick Reference
2. SDI II IP Core Overview
3. SDI II IP Core Getting Started
4. SDI II IP Core Parameters
5. SDI II IP Core Functional Description
6. SDI II IP Core Signals
7. SDI II IP Core Design Considerations
8. SDI II IP Core Testbench and Design Examples
9. SDI II Intel® FPGA IP User Guide Archives
10. Document Revision History for the SDI II Intel® FPGA IP User Guide

7.1.1.2. Modifying the Reconfiguration Management

Perform the following changes to modify the reconfiguration management:

  • Edit the Number_of_channels parameter in sdi_ii_ed_reconfig_mgmt.v. This parameter value should be the total number of the SDI RX channels declared in the design. In this example, the NUM_CHS is 3.
  • Link the interface signals—sdi_rx_start_reconfig, sdi_rx_reconfig_done, and sdi_rx_std—between multiple SDI instances and reconfiguration management block. Link the interface signals—sdi_tx_start_reconfig, sdi_tx_reconfig_done, and sdi_tx_pll_sel—between user and reconfiguration management block. You must link the signals in the order of the logical channel number (rx_log_ch_num and tx_log_ch_num) in the reconfiguration logic source file (sdi_ii_reconfig_logic.v). For example: 
wire tx_start_reconfig_ch2,tx_start_reconfig_ch1,tx_start_reconfig_ch0;
wire tx_pll_sel_ch2,tx_pll_sel_ch1,tx_pll_sel_ch0;
wire tx_reconfig_done_ch2,tx_reconfig_done _ch1,tx_reconfig_done_ch0;
wire rx_start_reconfig_ch2,rx_start_reconfig_ch1,rx_start_reconfig_ch0;
wire [1:0] rx_std_ch2, rx_std_ch1,rx_std_ch0;
wire rx_reconfig_done_ch2,rx_reconfig_done _ch1,rx_reconfig_done_ch0;

sdi_ii_ed_reconfig_mgmt #(
   . NUM_CHS (3),
) u_reconfig_mgmt (
   .sdi_tx_start_reconfig (tx_start_reconfig_ch2, tx_start_reconfig_ch1,tx_start_reconfig_ch0), 
   .sdi_tx_pll_sel  (tx_pll_sel_ch2,tx_pll_sel_ch1,tx_pll_sel_ch0),
   .sdi_tx_reconfig_done (tx_reconfig_done_ch2, tx_reconfig_done_ch1,tx_reconfig_done_ch0), 
   .sdi_rx_start_reconfig (rx_start_reconfig_ch2, rx_start_reconfig_ch1,rx_start_reconfig_ch0), 
   .sdi_rx_std   (rx_std_ch2,rx_std_ch1,rx_std_ch0),
   .sdi_rx_reconfig_done (rx_reconfig_done_ch2, rx_reconfig_done_ch1,rx_reconfig_done_ch0)
)
  • In the reconfiguration logic source file, the default setting for the wire rx_log_ch_num is 0 and 2 for channel 0 and channel 1, respectively. The default setting for the wire tx_log_ch_num is 0 and 2 (duplex) or 3 (TX) for channel 0 and channel 1, respectively. These numbers are referring to the Number_of_channels parameter value that was set in the transceiver reconfiguration controller. The logical channel number for each SDI channel is as listed in the table below.
Table 30.  Logical Channel Number for Each SDI Channel

SDI Channel

Direction

Number of Reconfiguration

Interfaces

Logical Channel Number

0

Duplex

2

  • 0: RX/TX channel
  • 1: Tx PLL

1

RX and TX

3 (1 for RX and 2 for TX)

  • 2: RX channel
  • 3: TX channel
  • 4: TX PLL

2

Duplex

2

  • 5: RX/TX channel
  • 6: TX PLL
  • Edit the reconfiguration logic source file to assign the logical channel number for the additional SDI duplex instance, which occupies the SDI Ch2. The logical channel number specified in the source file is the reconfiguration interface that is intended for dynamic reconfiguration. For example, if TX channel is intended for dynamic reconfiguration, tx_log_ch_num[2] should be 5. 
wire [7:0] rx_log_ch_num [0:NUM_CHS-1];
   assign rx_log_ch_num[0] = 8'd0; // Duplex Rx channel share same 
                                      logical channel number with Tx
   assign rx_log_ch_num[1] = 8'd2; // Rx channel
   assign rx_log_ch_num[2] = 8'd5; // Duplex Rx channel
   
wire [7:0] tx_log_ch_num [0:NUM_CHS-1];
   assign tx_log_ch_num[0] = 8'd0; // Duplex Tx channel share same 
                                      logical channel number with Rx
   assign tx_log_ch_num[1] = 8'd3; // Tx channel
   assign tx_log_ch_num[2] = 8'd5; // Duplex Tx channel
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