Intel® Quartus® Prime Pro Edition User Guide: Third-party Synthesis

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ID 683122
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Mentor Graphics Precision* Synthesis Support 2. Synopsys Synplify* Support A. Intel® Quartus® Prime Pro Edition User Guides
1. Mentor Graphics Precision* Synthesis Support x
1.1. About Precision RTL Synthesis Support 1.2. Design Flow 1.3. Intel Device Family Support 1.4. Precision Synthesis Generated Files 1.5. Creating and Compiling a Project in the Precision Synthesis Software 1.6. Mapping the Precision Synthesis Design 1.7. Synthesizing the Design and Evaluating the Results 1.8. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features 1.9. Mentor Graphics Precision* Synthesis Support Revision History
1.2. Design Flow x
1.2.1. Timing Optimization
1.6. Mapping the Precision Synthesis Design x
1.6.1. Setting Timing Constraints 1.6.2. Setting Mapping Constraints 1.6.3. Assigning Pin Numbers and I/O Settings 1.6.4. Assigning I/O Registers 1.6.5. Disabling I/O Pad Insertion 1.6.6. Controlling Fan-Out on Data Nets
1.6.5. Disabling I/O Pad Insertion x
1.6.5.1. Preventing the Precision Synthesis Software from Adding I/O Pads 1.6.5.2. Preventing the Precision Synthesis Software from Adding an I/O Pad on an Individual Pin
1.7. Synthesizing the Design and Evaluating the Results x
1.7.1. Obtaining Accurate Logic Utilization and Timing Analysis Reports
1.8. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features x
1.8.1. Instantiating IP Cores With IP Catalog-Generated Verilog HDL Files 1.8.2. Instantiating IP Cores With IP Catalog-Generated VHDL Files 1.8.3. Instantiating Intellectual Property With the IP Catalog and Parameter Editor 1.8.4. Instantiating Black Box IP Functions With Generated Verilog HDL Files 1.8.5. Instantiating Black Box IP Functions With Generated VHDL Files 1.8.6. Inferring Intel FPGA IP Cores from HDL Code
1.8.6. Inferring Intel FPGA IP Cores from HDL Code x
1.8.6.1. Multipliers 1.8.6.2. Setting the Use Dedicated Multiplier Option 1.8.6.3. Setting the dedicated_mult Attribute 1.8.6.4. Multiplier-Accumulators and Multiplier-Adders 1.8.6.5. Controlling DSP Block Inference 1.8.6.6. RAM and ROM
1.8.6.1. Multipliers x
1.8.6.1.1. Controlling DSP Block Inference for Multipliers
2. Synopsys Synplify* Support x
2.1. About Synplify Support 2.2. Design Flow 2.3. Hardware Description Language Support 2.4. Intel Device Family Support 2.5. Tool Setup 2.6. Synplify Software Generated Files 2.7. Design Constraints Support 2.8. Simulation and Formal Verification 2.9. Synplify Optimization Strategies 2.10. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features 2.11. Synopsys Synplify* Support Revision History 2.12. Intel Quartus Prime Pro Edition User Guide: Third-Party Synthesis Archives
2.5. Tool Setup x
2.5.1. Specifying the Intel® Quartus® Prime Software Version
2.7. Design Constraints Support x
2.7.1. Running the Intel® Quartus® Prime Software Manually With the Synplify-Generated Tcl Script 2.7.2. Passing Timing Analyzer SDC Timing Constraints to the Intel® Quartus® Prime Software
2.7.2. Passing Timing Analyzer SDC Timing Constraints to the Intel® Quartus® Prime Software x
2.7.2.1. Individual Clocks and Frequencies 2.7.2.2. Input and Output Delay 2.7.2.3. Multicycle Path 2.7.2.4. False Path
2.9. Synplify Optimization Strategies x
2.9.1. Using Synplify Premier to Optimize Your Design 2.9.2. Using Implementations in Synplify Pro or Premier 2.9.3. Timing-Driven Synthesis Settings 2.9.4. FSM Compiler 2.9.5. Optimization Attributes and Options 2.9.6. Intel-Specific Attributes
2.9.3. Timing-Driven Synthesis Settings x
2.9.3.1. Clock Frequencies 2.9.3.2. Multiple Clock Domains 2.9.3.3. Input and Output Delays 2.9.3.4. Multicycle Paths 2.9.3.5. False Paths
2.9.4. FSM Compiler x
2.9.4.1. FSM Explorer in Synplify Pro and Premier
2.9.5. Optimization Attributes and Options x
2.9.5.1. Retiming in Synplify Pro and Premier 2.9.5.2. Maximum Fan-Out 2.9.5.3. Preserving Nets 2.9.5.4. Register Packing 2.9.5.5. Resource Sharing 2.9.5.6. Preserving Hierarchy 2.9.5.7. Register Input and Output Delays 2.9.5.8. syn_direct_enable 2.9.5.9. I/O Standard
2.9.6. Intel-Specific Attributes x
2.9.6.1. altera_chip_pin_lc 2.9.6.2. altera_io_powerup 2.9.6.3. altera_io_opendrain
2.10. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features x
2.10.1. Instantiating Intel FPGA IP Cores with the IP Catalog 2.10.2. Including Files for Intel® Quartus® Prime Placement and Routing Only 2.10.3. Inferring Intel FPGA IP Cores from HDL Code
2.10.1. Instantiating Intel FPGA IP Cores with the IP Catalog x
2.10.1.1. Instantiating Intel FPGA IP Cores with IP Catalog Generated Verilog HDL Files 2.10.1.2. Instantiating Intel FPGA IP Cores with IP Catalog Generated VHDL Files 2.10.1.3. Changing Synplify’s Default Behavior for Instantiated Intel FPGA IP Cores 2.10.1.4. Instantiating Intellectual Property with the IP Catalog and Parameter Editor 2.10.1.5. Instantiating Black Box IP Cores with Generated Verilog HDL Files 2.10.1.6. Instantiating Black Box IP Cores with Generated VHDL Files 2.10.1.7. Other Synplify Software Attributes for Creating Black Boxes
2.10.3. Inferring Intel FPGA IP Cores from HDL Code x
2.10.3.1. Inferring Multipliers 2.10.3.2. Inferring RAM 2.10.3.3. RAM Initialization 2.10.3.4. Inferring ROM 2.10.3.5. Inferring Shift Registers
2.10.3.1. Inferring Multipliers x
2.10.3.1.1. Resource Balancing 2.10.3.1.2. Controlling the DSP Block Inference 2.10.3.1.3. Signal Level Attribute
1. Mentor Graphics Precision* Synthesis Support
2. Synopsys Synplify* Support
A. Intel® Quartus® Prime Pro Edition User Guides

1.6. Mapping the Precision Synthesis Design

In the next steps, you set constraints and map the design to technology‑specific cells. The Precision Synthesis software maps the design by default to the fastest possible implementation that meets your timing constraints. To accomplish this, you must specify timing requirements for the automatically determined clock sources. With this information, the Precision Synthesis software performs static timing analysis to determine the location of the critical timing paths. The Precision Synthesis software achieves the best results for your design when you set as many realistic constraints as possible. Be sure to set constraints for timing, mapping, false paths, multicycle paths, and other factors that control the structure of the implemented design.

Mentor Graphics recommends creating an .sdc file and adding this file to the Constraint Files section of the Project Files list. You can create this file with a text editor, by issuing command-line constraint parameters, or by directing the Precision Synthesis software to generate the file automatically the first time you synthesize your design. By default, the Precision Synthesis software saves all timing constraints and attributes in two files: precision_rtl.sdc and precision_tech.sdc. The precision_rtl.sdc file contains constraints set on the RTL-level database (post-compilation) and the precision_tech.sdc file contains constraints set on the gate-level database (post- synthesis) located in the current implementation directory.

You can also enter constraints at the command line. After adding constraints at the command line, update the .sdc file with the update constraint file command. You can add constraints that change infrequently directly to the HDL source files with HDL attributes or pragmas.

Note: The Precision .sdc file contains all the constraints for the Precision Synthesis project. For the Intel® Quartus® Prime software, placement constraints are written in a .tcl file and timing constraints for the Timing Analyzer are written in the Intel® Quartus® Prime .sdc file.

Section Content
Setting Timing Constraints
Setting Mapping Constraints
Assigning Pin Numbers and I/O Settings
Assigning I/O Registers
Disabling I/O Pad Insertion
Controlling Fan-Out on Data Nets

Level Two Title