AN 736: Nios II Processor Booting From Altera Serial Flash (EPCQ)

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ID 683104
Date 5/20/2016
Public
Document Table of Contents
Document Table of Contents x
1. Nios II Processor Booting From Altera Serial Flash (EPCQ)
1. Nios II Processor Booting From Altera Serial Flash (EPCQ) x
1.1. Definitions 1.2. Description of the Altera Serial Flash Controller 1.3. Scenarios for Booting Nios II from EPCQ Flash 1.4. Nios II Processor Configuration and Boot Flow 1.5. Steps to Build a Bootable System 1.6. EPCQ HAL Driver 1.7. Nios II Processor Booting Elements 1.8. Revision History for Nios II Booting From Altera Serial Flash (EPCQ)
1.3. Scenarios for Booting Nios II from EPCQ Flash x
1.3.1. Nios II Processor Application Execute-In-Place from EPCQ Flash 1.3.2. Nios II Processor Application Copied from EPCQ Flash to RAM
1.5. Steps to Build a Bootable System x
1.5.1. Design 1.5.2. Configuration and Compilation 1.5.3. BSP Editor Settings 1.5.4. Application 1.5.5. Programming Files Conversion 1.5.6. Configuration for EPCQ Programming 1.5.7. Download 1.5.8. Reset and Boot
1.5.2. Configuration and Compilation x
1.5.2.1. Reset and Exception Vector Settings for Nios® II Execute-In-Place Method 1.5.2.2. Reset and Exception Vector Settings for Nios II Boot Copier Method
1.7. Nios II Processor Booting Elements x
1.7.1. Memcpy-based Nios II Boot Copier
1. Nios II Processor Booting From Altera Serial Flash (EPCQ)

1.5.2.1. Reset and Exception Vector Settings for Nios® II Execute-In-Place Method

  1. Under Reset Vector in the Vectors tab, select EPCQ (epcq_controller_0.avl_mem) in the Reset vector memory drop-down menu and type the reset vector offset in the Reset vector offset entry box. The reset vector must be the base address of your application. In this example, it is 0x01E00000.
    Note:

    Your *.sof image size influences your reset vector offset configuration. The reset vector offset is the start address of the .hex file in EPCQ flash and it must point to a location after the *.sof image. You can determine the minimum reset vector offset by using the following equation:

    minimum reset vector offset= (.sof image start address + .sof image size) in HEX

    For example, if your *.sof image starts at address 0x0 and is 512 KB in size, then the minimum reset vector offset location you can select is 0x0080000. If the *.sof image space and the reset vector offset location overlap, Intel® Quartus® Prime software displays an overlap error.

  2. Under Exception Vector, you may select EPCQ (epcq_controller_0.avl_mem) or OCRAM in the Exception vector memory drop-down menu. In this example, 0x20 is listed for the Exception vector offset entry.
    Note: When executing-in-place, the Nios® II processor boots and runs directly from EPCQ flash, without copying any code at boot time. Because the Nios® II begins executing at the reset address in this case, exception vectors must be located at a nonzero exception vector offset to allow for instructions between the reset vector and the base of the exception vectors. Thus, you must include an exception vector offset when the reset vector and the exception vector point to the same memory and no boot copier is present.
    Note: Intel® recommends setting the exception vector to OCRAM to make the interrupt processing faster.
    Figure 4. Exception Vector Settings in Platform Designer
  3. Click Finish. You will return to the Platform Designer System Contents tab.
  4. Double-click on the Serial Flash Controller IP to open the Intel FPGA Serial Flash Controller Parameter editor.
  5. Select the Configuration device type based on your hardware design and choose the desired I/O mode.
  6. Close the Parameter Editor and return to the Platform Designer System Contents tab.
  7. Click Generate HDL to generate your Platform Designer design.
  8. Compile your design in Intel® Quartus® Prime software.
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