AN 736: Nios II Processor Booting From Altera Serial Flash (EPCQ)

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ID 683104
Date 5/20/2016
Public
Document Table of Contents
Document Table of Contents x
1. Nios II Processor Booting From Altera Serial Flash (EPCQ)
1. Nios II Processor Booting From Altera Serial Flash (EPCQ) x
1.1. Definitions 1.2. Description of the Altera Serial Flash Controller 1.3. Scenarios for Booting Nios II from EPCQ Flash 1.4. Nios II Processor Configuration and Boot Flow 1.5. Steps to Build a Bootable System 1.6. EPCQ HAL Driver 1.7. Nios II Processor Booting Elements 1.8. Revision History for Nios II Booting From Altera Serial Flash (EPCQ)
1.3. Scenarios for Booting Nios II from EPCQ Flash x
1.3.1. Nios II Processor Application Execute-In-Place from EPCQ Flash 1.3.2. Nios II Processor Application Copied from EPCQ Flash to RAM
1.5. Steps to Build a Bootable System x
1.5.1. Design 1.5.2. Configuration and Compilation 1.5.3. BSP Editor Settings 1.5.4. Application 1.5.5. Programming Files Conversion 1.5.6. Configuration for EPCQ Programming 1.5.7. Download 1.5.8. Reset and Boot
1.5.2. Configuration and Compilation x
1.5.2.1. Reset and Exception Vector Settings for Nios® II Execute-In-Place Method 1.5.2.2. Reset and Exception Vector Settings for Nios II Boot Copier Method
1.7. Nios II Processor Booting Elements x
1.7.1. Memcpy-based Nios II Boot Copier
1. Nios II Processor Booting From Altera Serial Flash (EPCQ)

1.5.1. Design

  1. Create your Nios® II processor project using Quartus II and Qsys.
  2. Add the Intel® Serial Flash Controller IP to your Qsys system. Refer to the diagram below for the IP connection in Qsys.
    Figure 3. Altera Serial Flash Controller IP Connections in Qsys
    Note: The maximum input clock for Intel® Serial Flash Controller IP is 25 MHz. The input clock must not exceed this maximum value.
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