Altera® Quartus® Prime Standard Edition Settings File Reference Manual
Visible to Intel only — GUID: row1489537869048
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Visible to Intel only — GUID: row1489537869048
Ixiasoft
1.10.8. ASYNC_PIPELINE_REG_REACH
Specify the maximum number of LABs that the asynchronous signal sourcing at the To register can go across before a new pipeline register is inserted. This requirement might not be met for all pipeline stages, when, due to congestion or over-filled LABs, the register cannot be placed at the desired location
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
Syntax
set_global_assignment -name ASYNC_PIPELINE_REG_REACH -entity <entity name> <value> set_instance_assignment -name ASYNC_PIPELINE_REG_REACH -to <to> -entity <entity name> <value>