Altera® Quartus® Prime Standard Edition Settings File Reference Manual
Visible to Intel only — GUID: rpe1489537691098
Ixiasoft
Visible to Intel only — GUID: rpe1489537691098
Ixiasoft
1.2.9. ALLOW_XOR_GATE_USAGE
Allows the Compiler to use the XOR gate that exists in a macrocell (that is, in an embedded cell within an Embedded System Block [ESB] that is set to use Product Term mode). This option is ignored if you select 'LUT' or 'ROM' as the setting for the Technology Mapper option.
Type
Boolean
Device Support
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_XOR_GATE_USAGE <value>
set_global_assignment -name ALLOW_XOR_GATE_USAGE -entity <entity name> <value>
set_instance_assignment -name ALLOW_XOR_GATE_USAGE -to <to> -entity <entity name> <value>
Default Value
On
Example
set_instance_assignment -name allow_xor_gate_usage off -to clock