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1.1. List of Abbreviations
1.2. Introduction
1.3. Intel® Stratix® 10 Early Power Estimator Tool (EPE)
1.4. Intel® Stratix® 10 FPGA Package Physical Design
1.5. Physical Package Structure
1.6. Intel® Stratix® 10 FPGA Thermal Design Parameters
1.7. Intel® Stratix® 10 Compact Thermal Model (CTM)
1.8. Intel® Stratix® 10 Temperature Sensing Diodes (TSD)
1.9. Intel® Stratix® 10 Thermal Design Process
1.10. Early Power Estimator (EPE)
1.11. Transceiver Channel Spreading
1.12. Thermal Parameter Dependencies
1.13. Intel® Stratix® 10 Thermal Design Example
1.14. Document Revision History for AN 787: Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator
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1.13.3. Transceiver Channel Placement Optimization
In some designs, it might be possible to further reduce the transceiver temperatures by spreading the channels to reduce the power density. For example, in the above design the HSSI_2_0 transceiver has 8 high speed transceiver channels that are laid out in half of the die. The effect of spreading these channels to all the die area can be shown in the EPE by the following transceiver placement.
The new placement relaxes the cooling requirement from a ΨCA of 0.332 to 0.342 °C/W and now the core fabric die has the highest ΨJC. Repeating the CFD analysis using the original cooling solution with the new power dissipations results in the following IHS temperature results.
Calculating the new junction temperatures with the updated power values and CFD results:
HSSI_2_0 die temperature: TJ = 84 + (150 * 0.042) = 90.3 °C
Core fabric temperature: TJ = 84 + (150 * 0.052) = 91.8 °C
This example demonstrates that the channel spreading could reduce the cooling requirement or result in lower junction temperatures for the same cooling solution.