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1.1. List of Abbreviations
1.2. Introduction
1.3. Intel® Stratix® 10 Early Power Estimator Tool (EPE)
1.4. Intel® Stratix® 10 FPGA Package Physical Design
1.5. Physical Package Structure
1.6. Intel® Stratix® 10 FPGA Thermal Design Parameters
1.7. Intel® Stratix® 10 Compact Thermal Model (CTM)
1.8. Intel® Stratix® 10 Temperature Sensing Diodes (TSD)
1.9. Intel® Stratix® 10 Thermal Design Process
1.10. Early Power Estimator (EPE)
1.11. Transceiver Channel Spreading
1.12. Thermal Parameter Dependencies
1.13. Intel® Stratix® 10 Thermal Design Example
1.14. Document Revision History for AN 787: Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator
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1.8. Intel® Stratix® 10 Temperature Sensing Diodes (TSD)
Each die in an Intel® Stratix® 10 FPGA device contains a Temperature Sensing Diode (TSD). Intel® provides a Temperature Sensor IP core to obtain the temperature of each die. However, with flexibility in Intel® Stratix® 10 devices, the location of hot spots on the transceiver die may vary based on your application, and it may not always be in the same location as the temperature sensor. Therefore, a temperature sensor may not report the actual temperature of the hot spot. The EPE calculates the offset values for each transceiver die and reports them on its Thermal worksheet. Addition of these values to the temperatures reported by the appropriate TSDs results in the correct values for the maximum junction temperature of each die. The accuracy of the TSD is +/- 5°C. Therefore, you may need to adjust the TJ-MAX for some designs to ensure the threshold temperature is never crossed.