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1.1. List of Abbreviations
1.2. Introduction
1.3. Intel® Stratix® 10 Early Power Estimator Tool (EPE)
1.4. Intel® Stratix® 10 FPGA Package Physical Design
1.5. Physical Package Structure
1.6. Intel® Stratix® 10 FPGA Thermal Design Parameters
1.7. Intel® Stratix® 10 Compact Thermal Model (CTM)
1.8. Intel® Stratix® 10 Temperature Sensing Diodes (TSD)
1.9. Intel® Stratix® 10 Thermal Design Process
1.10. Early Power Estimator (EPE)
1.11. Transceiver Channel Spreading
1.12. Thermal Parameter Dependencies
1.13. Intel® Stratix® 10 Thermal Design Example
1.14. Document Revision History for AN 787: Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator
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1.2. Introduction
An Intel® Stratix® 10 device has a Multi-Chip Module (MCM) structure. It can contain between two and nine dies. One die is always the main FPGA core fabric die, and there can be between one and six transceiver dies, and up to two High Bandwidth Memory (HBM) dies. Due to complex construction and no uniform power density in some of the dies, the thermal engineering of an Intel® Stratix® 10 device requires a specific process and familiarity with the following: