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1.1. List of Abbreviations
1.2. Introduction
1.3. Intel® Stratix® 10 Early Power Estimator Tool (EPE)
1.4. Intel® Stratix® 10 FPGA Package Physical Design
1.5. Physical Package Structure
1.6. Intel® Stratix® 10 FPGA Thermal Design Parameters
1.7. Intel® Stratix® 10 Compact Thermal Model (CTM)
1.8. Intel® Stratix® 10 Temperature Sensing Diodes (TSD)
1.9. Intel® Stratix® 10 Thermal Design Process
1.10. Early Power Estimator (EPE)
1.11. Transceiver Channel Spreading
1.12. Thermal Parameter Dependencies
1.13. Intel® Stratix® 10 Thermal Design Example
1.14. Document Revision History for AN 787: Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator
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1.14. Document Revision History for AN 787: Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator
Document Version | Changes |
---|---|
2021.07.16 | Modified document title to Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator. |
2018.08.20 | In Section 1.2, Introduction, changed an Intel® Stratix® 10 device "can contain between two and seven dies" to "can contain between two and nine dies" |
2018.01.26 | Updated to account for changes in the latest EPE with HBM and E-Tile updates |
2017.06.19 | Added methodology to use the Thermal worksheet of the EPE tool |
2017.02.03 | Initial release. |