AN 803: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

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ID 683077
Date 2/06/2020
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Document Table of Contents
Document Table of Contents x
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core x
ADC- Intel® Arria® 10 Multi-Link Design Overview ADC- Intel® Arria® 10 Multi-Link Design Implementation Guidelines Synchronized ADC- Intel® Arria® 10 Multi-Link Unsynchronized ADC- Intel® Arria® 10 Multi-Link Migrating the RX Multi-Link Design from Simulation to Synthesis Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core
Synchronized ADC- Intel® Arria® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Simulation Testbench for Synchronized ADC- Intel® Arria® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Synchronized ADC- Intel® Arria® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Unsynchronized ADC- Intel® Arria® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Testbench for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Migrating the RX Multi-Link Design from Simulation to Synthesis x
Migrating RX Platform Designer System for Simulation to RX Platform Designer System for Synthesis Migrating RX Top-Level HDL for Simulation to RX Top-Level HDL for Synthesis
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

Viewing the Simulation Results

The simulation testbench prints the results at the transcript or terminal where you execute the simulation script. The following example shows the printout and waveform of the simulation in ModelSim‐ Intel® FPGA Edition:

If the simulation passes, the transcript section prints TESTBENCH_PASSED: SIM PASSED! as shown in the following figure.

Figure 6. Figure 11. ModelSim‐ Intel® FPGA Edition Simulation Results Transcript

If the simulation fails, the transcript section prints TESTBENCH_FAILED: SIM FAILED! along with the failure reason.

If you want to view the waveform, the following are the explanations of a series of events during the link initialization.

  1. After the /tb_top/rst is de-asserted, the transceiver reset controller sequences the reset for the transceiver in both Link 0 and Link 1 JESD204B IP core.
  2. The /tb_top/xcvr_rst_ctrl_tx_ready is asserted when the TX transceiver channels and TX PLL are out of reset.
    Figure 7. Figure 12. ModelSim‐ Intel® FPGA Edition Simulation Waveform during Global Reset De-assertion
  3. The TX channels send data to RX channels.
  4. When the RX channels recovered the data and clock successfully, the /tb_top/xcvr_rst_ctrl_rx_ready is asserted.
  5. The reset sequencer in the Platform Designer system de-asserts the jesd204_rx_avs_rst_n so that the Avalon-MM BFM master configures the test mode CSR.
  6. The reset sequencer de-asserts the rxlink_rst_n_reset_n and the IP core is out of reset.
  7. The RX transport layer asserts the jesd204_rx_link_ready to IP core.
  8. The testbench sends a rx_sysref pulse to the IP core.
  9. The IP core de-assert the dev_sync_n.
  10. After the IP core exits the code group synchronization (CGS) phase, the IP core enters the initial lane alignment sequence (ILAS) phase.
  11. The alldev_lane_aligned is asserted when both IP cores achieve lane alignment.
  12. The jesd204_rx_link_valid is asserted when the IP core enters the user data phase and sample data is sent to RX transport layer.
  13. The RX transport layer performs the lane mapping of the sample data.
  14. The pattern checker checks the received sample data from RX transport layer.
  15. No data error is detected by the pattern checker and no interrupt is asserted by both the RX and TX IP cores.
  16. The testbench asserts the test_passed flag when the above conditions in item 15 are met.
    Figure 8. Figure 13. ModelSim‐ Intel® FPGA Edition Simulation Waveform for Successful Link Initialization
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