AN 803: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

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ID 683077
Date 2/06/2020
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Document Table of Contents
Document Table of Contents x
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core x
ADC- Intel® Arria® 10 Multi-Link Design Overview ADC- Intel® Arria® 10 Multi-Link Design Implementation Guidelines Synchronized ADC- Intel® Arria® 10 Multi-Link Unsynchronized ADC- Intel® Arria® 10 Multi-Link Migrating the RX Multi-Link Design from Simulation to Synthesis Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core
Synchronized ADC- Intel® Arria® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Simulation Testbench for Synchronized ADC- Intel® Arria® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Synchronized ADC- Intel® Arria® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Unsynchronized ADC- Intel® Arria® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Testbench for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Migrating the RX Multi-Link Design from Simulation to Synthesis x
Migrating RX Platform Designer System for Simulation to RX Platform Designer System for Synthesis Migrating RX Top-Level HDL for Simulation to RX Top-Level HDL for Synthesis
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

Editing TX Simulation Model Platform Designer System for Synchronized ADC- Intel® Arria® 10 Multi-Link

  1. Open the top-level system, altera_jesd204_ed_qsys_TX.qsys, in Platform Designer.
    1. The TX .qsys file is located at ed_sim/testbench/sim_models/ folder.
    2. To open the .qsys file in Platform Designer, you must have an associated Intel® Quartus® Prime project. Copy the altera_jesd204_ed_RX.qpf and altera_jesd204_ed_RX.qsf files from the ed_synth folder into ed_sim/testbench/sim_models folder.
    3. Select the altera_jesd204_ed_RX.qpf and click Open.
    4. The IP Synchronization Result window opens and click OK to proceed.
  2. In the System Contents tab, right-click the altera_jesd204_subsystem_TX instance and select Drill into Subsystem. This opens the altera_jesd204b_subsystem_TX.qsys Platform Designer subsystem.
  3. Right-click the altera_jesd204_TX component and select Duplicate to duplicate the JESD204B IP core. You can rename the duplicated IP core as altera_jesd204_TX1.
    Note: Select No if the Platform Designer prompts Do you want to also duplicate the IP Variant file on the disk?. This is because the duplicated JESD204B IP core has the same parameters as the original JESD204B IP core.
  4. Connect the duplicated IP core port as shown in the following table.
    Ports for Duplicated IP Core Connection
    jesd204_tx_avs mm_bridge.m0
    jesd204_tx_avs_clk mgmt_clk.clk
    jesd204_tx_avs_rst_n reset_seq.reset_out2
    txlink_clk link_clk.clk
  5. Export the rest of the ports to the top-level Platform Designer system. To export a port, click the Double-click to export in the Export column of the System Contents tab.
  6. At the altera_jesd204_TX component, disconnect the connections at the following ports. Export them to the top-level Platform Designer system.
    • dev_sync_n
    • mdev_sync_n
    • tx_analogreset
    • tx_digitalreset
    • tx_cal_busy
  7. Change the number of transceiver channels in the Transceiver PHY reset controller to the total number of transceiver channels of all the JESD204B IP cores in the altera_jesd204_subsystem_TX.
  8. Export the following ports from the Transceiver PHY reset controller:
    1. tx_analogreset
    2. tx_digitalreset
    3. tx_cal_busy
  9. At the Address Map, adjust the starting address of altera_jesd204_TX1 interface so that there is no conflict with other components. For example, you can set the starting address of altera_jesd204_TX1 IP core to 0x000c_0400 as shown in the following table.
    Table 4.  Synchronized ADC-FPGA Multi-Link TX Platform Designer Simulation Model Address Map for System Console Control Path (PHY Dynamic Reconfiguration Disabled)
      mm_bridge.m0
    altera_jesd204_TX.jesd204_tx_avs 0x000c_0000 – 0x000c_03ff
    altera_jesd204_TX1.jesd204_tx_avs 0x000c_0400 – 0x000c_07ff
    Table 5.  Synchronized ADC-FPGA Multi-Link TX Platform Designer Simulation Model Address Map for System Console Control Path (PHY Dynamic reconfiguration Enabled)
      mm_bridge.m0
    altera_jesd204_TX.jesd204_tx_avs 0x000c_0000 – 0x000c_03ff
    altera_jesd204_TX.reconfig_avmm 0x0000_0000 – 0x0000_1fff
    altera_jesd204_TX1.jesd204_tx_avs 0x000c_0400 – 0x000c_07ff
    altera_jesd204_TX1.reconfig_avmm 0x0000_2000 – 0x0000_3fff
  10. Repeat step 3 until step 9 for subsequent links in your design.
  11. Go up to the top-level Platform Designer system.
  12. Connect the high speed serial clock ports of the duplicated TX IP core to the ATX PLL mgcb_serial_clk port. Example of 2 transceiver channels IP core:
    • altera_jesd204_tx1_tx_serial_clk0_ch0
    • altera_jesd204_tx1_tx_serial_clk0_ch1
  13. Export the unconnected ports of altera_jesd204_subsystem_TX instance.
  14. Click Generate HDL.
  15. Ensure you select the HDL language of your choice in the Simulation section of the Generation windows to generate the simulation models.
  16. Click Generate and Yes to save and generate the design files needed for simulation.
  17. After the HDL generation is completed, select Generate from the menu, select Show Instantiation Template… and click Copy.
  18. Paste the instantiation template of altera_jesd204_ed_qsys_TX Platform Designer to a text editor.
    You must update the instantiated Platform Designer ports at the top-level HDL.
  19. Click Finish to save your Platform Designer settings and exit the Platform Designer window.
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