Visible to Intel only — GUID: mwh1410383659802
Ixiasoft
Visible to Intel only — GUID: mwh1410383659802
Ixiasoft
2.2.5. Step 5: Analyze Timing Analysis Results
The Timing Analyzer provides very fine-grained reporting and analysis capabilities to identify and correct violations along timing paths. Generate timing reports to view how to best optimize the critical paths in your design. If you modify, remove, or add constraints, re-run timing analysis. This iterative process helps resolve timing violations in your design.
Reports that indicate failing timing performance appear in red text, reports that pass appear in black text. A gold question mark icon indicates reports that are outdated due to SDC changes since generation. Regenerate these reports to show the latest data.
The following sections describe how to generate various timing reports for analysis.