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Ixiasoft
2.3.1. Recommended Initial SDC Constraints
2.3.2. SDC File Precedence
2.3.3. Iterative Constraint Modification
2.3.4. Creating Clocks and Clock Constraints
2.3.5. Creating I/O Constraints
2.3.6. Creating Delay and Skew Constraints
2.3.7. Creating Timing Exceptions
2.3.8. Example Circuit and SDC File
2.3.7.5.1. Default Multicycle Analysis
2.3.7.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.3.7.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.3.7.5.4. Same Frequency Clocks with Destination Clock Offset
2.3.7.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.3.7.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.3.7.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.3.7.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
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Ixiasoft
2.2.5.1. Timing Report Commands
The Timing Analyzer generates only a subset of all available reports by default, including the Timing Analyzer Summary report. However, you can generate many other detailed reports in the Timing Analyzer GUI, or with command-line commands. You can customize the display of information in the reports.
Timing Analyzer Tasks Pane GUI | Command-Line | Generates |
---|---|---|
Custom Reports > Report Timing | report_timing | Timing report |
Custom Reports > Report Exceptions | report_exceptions | Exceptions report |
Diagnostic > Report Clock Transfers | report_clock_transfers | Clock Transfers report |
Slack > Report Minimum Pulse Width Summary | report_min_pulse_width | Minimum Pulse Width Summary report |
Diagnostic > Report Unconstrained Paths | report_ucp | Unconstrained Paths report |