Visible to Intel only — GUID: mwh1414613513009
Ixiasoft
Visible to Intel only — GUID: mwh1414613513009
Ixiasoft
2.2.5.5. Correlating Constraints to the Timing Report
The following figures show the results of running Report Timing on a particular path.
create_clock -name clocktwo -period 10.000 [get_ports {clk2}]
set_multicycle_path -from clocktwo -to clocktwo -setup -end 2 set_multicycle_path -from clocktwo -to clocktwo -hold -end 1
The set_max_delay and set_min_delay constraints explicitly override the setup relationship. Note that the only thing changing for these different constraints are the launch edge time and latch edge times for setup and hold analysis. Every other line item comes from delays inside the FPGA and are static for a given fit. View these reports to analyze how your constraints affect the timing reports.
For I/O, you must add the -max and -min values. They are display as iExt or oExt in the Type column. An example is an output port with a set_output_delay -max 1.0 and set_output_delay -min -0.5:
The clock relationships determine the launch and latch edge times, multicycles, and possibly set_max_delay or set_min_delay constraints. The Timing Analyzer also adds the value of set_output_delay as an oExt value. For outputs this value is part of the Data Required Path, since this is the external part of the analysis. The setup report on the left subtracts the -max value, making the setup relationship harder to meet, since the Data Arrival Path must be shorter than the Data Required Path. The Timing Analyzer also subtracts the -min value. This subtraction is why a negative number causes more restrictive hold timing. The Data Arrival Path must be longer than the Data Required Path.