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2.3.1. Recommended Initial SDC Constraints
2.3.2. SDC File Precedence
2.3.3. Iterative Constraint Modification
2.3.4. Creating Clocks and Clock Constraints
2.3.5. Creating I/O Constraints
2.3.6. Creating Delay and Skew Constraints
2.3.7. Creating Timing Exceptions
2.3.8. Example Circuit and SDC File
2.3.7.5.1. Default Multicycle Analysis
2.3.7.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.3.7.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.3.7.5.4. Same Frequency Clocks with Destination Clock Offset
2.3.7.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.3.7.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.3.7.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.3.7.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
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2.2.5.6. Locating Timing Paths in Other Tools
You can locate from paths and elements in the Timing Analyzer to other tools in the Intel® Quartus® Prime software.
You can right-click most paths or node names in the Timing Analyzer GUI and click the Locate or Locate Path commands. Use these commands in the Timing Analyzer GUI or the locate command in the Tcl console to locate to that node in other Intel® Quartus® Prime tools.
The following examples show how to locate the ten paths with the worst timing slack from Timing Analyzer to the Technology Map Viewer, and locate all ports matching data* in the Chip Planner.
Locating from the Timing Analyzer
# Locate in the Technology Map Viewer the ten paths with the worst slack locate [get_timing_paths -npaths 10] -tmv # locate all ports that begin with data in the Chip Planner locate [get_ports data*] -chip