P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 683059
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express 2. IP Architecture and Functional Description 3. Advanced Features 4. Interfaces 5. Parameters 6. Testbench 7. Troubleshooting/Debugging 8. P-tile Avalon® Streaming Intel FPGA IP for PCI Express* User Guide Archives 9. Document Revision History for the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide A. Configuration Space Registers B. Root Port Enumeration C. Implementation of Address Translation Services (ATS) in Endpoint Mode D. Packets Forwarded to the User Application in TLP Bypass Mode E. Using the Avery BFM for Intel P-Tile PCI Express Gen4 x16 Simulations F. Bifurcated Endpoint Support for Independent Warm Resets G. Margin Masks for the P-Tile Avalon Streaming Intel FPGA IP for PCI Express
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express x
1.1. Overview 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Performance and Resource Utilization 1.6. IP Core and Design Example Support Levels
1.1. Overview x
1.1.1. Standards and Specifications Compliance
2. IP Architecture and Functional Description x
2.1. Architecture 2.2. Functional Description
2.1. Architecture x
2.1.1. Clock Domains 2.1.2. Refclk 2.1.3. Reset
2.1.3. Reset x
2.1.3.1. Independent PERST
2.2. Functional Description x
2.2.1. PMA/PCS 2.2.2. Data Link Layer Overview 2.2.3. Transaction Layer Overview
3. Advanced Features x
3.1. PCIe* Port Bifurcation and PHY Channel Mapping 3.2. Virtualization Support 3.3. TLP Bypass Mode
3.2. Virtualization Support x
3.2.1. SR-IOV Support 3.2.2. VirtIO Support
3.2.1. SR-IOV Support x
3.2.1.1. SR-IOV Supported Features List 3.2.1.2. Implementation 3.2.1.3. VF to PF Mapping 3.2.1.4. Function Level Reset (FLR)
3.2.1.2. Implementation x
3.2.1.2.1. VF Error Flag Interface (for x16/x8 Cores Only)
3.2.2. VirtIO Support x
3.2.2.1. VirtIO Supported Features List 3.2.2.2. Overview 3.2.2.3. Parameters 3.2.2.4. VirtIO PCI Configuration Access Interface 3.2.2.5. Registers
3.2.2.5. Registers x
3.2.2.5.1. VirtIO Common Configuration Capability Register (Address: 0x012) 3.2.2.5.2. VirtIO Common Configuration BAR Indicator Register (Address: 0x013) 3.2.2.5.3. VirtIO Common Configuration BAR Offset Register (Address: 0x014) 3.2.2.5.4. VirtIO Common Configuration Structure Length Register (Address 0x015) 3.2.2.5.5. VirtIO Notifications Capability Register (Address: 0x016) 3.2.2.5.6. VirtIO Notifications BAR Indicator Register (Address: 0x017) 3.2.2.5.7. VirtIO Notifications BAR Offset Register (Address: 0x018) 3.2.2.5.8. VirtIO Notifications Structure Length Register (Address: 0x019) 3.2.2.5.9. VirtIO Notifications Notify Off Multiplier Register (Address: 0x01A) 3.2.2.5.10. VirtIO ISR Status Capability Register (Address: 0x02F) 3.2.2.5.11. VirtIO ISR Status BAR Indicator Register (Address: 0x030) 3.2.2.5.12. VirtIO ISR Status BAR Offset Register (Address: 0x031) 3.2.2.5.13. VirtIO ISR Status Structure Length Register (Address: 0x032) 3.2.2.5.14. VirtIO Device Specific Capability Register (Address: 0x033) 3.2.2.5.15. VirtIO Device Specific BAR Indicator Register (Address: 0x034) 3.2.2.5.16. VirtIO Device Specific BAR Offset Register (Address 0x035 ) 3.2.2.5.17. VirtIO Device Specific Structure Length Register (Address: 0x036) 3.2.2.5.18. VirtIO PCI Configuration Access Capability Register (Address: 0x037) 3.2.2.5.19. VirtIO PCI Configuration Access BAR Indicator Register (Address: 0x038) 3.2.2.5.20. VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039) 3.2.2.5.21. VirtIO PCI Configuration Access Structure Length Register (Address: 0x03A) 3.2.2.5.22. VirtIO PCI Configuration Access Data Register (Address: 0x03B)
3.3. TLP Bypass Mode x
3.3.1. Overview 3.3.2. Register Settings for the TLP Bypass Mode 3.3.3. User Avalon® -MM Interface 3.3.4. Avalon® -ST Interface
3.3.2. Register Settings for the TLP Bypass Mode x
3.3.2.1. TLPBYPASS_ERR_EN (Address 0x104194) 3.3.2.2. TLPBYPASS_ERR_STATUS (Address 0x104190)
3.3.4. Avalon® -ST Interface x
3.3.4.1. Configuration TLP 3.3.4.2. Transmit Interface 3.3.4.3. Receive Interface 3.3.4.4. Malformed TLP 3.3.4.5. ECRC
4. Interfaces x
4.1. Overview 4.2. Clocks and Resets 4.3. Serial Data Interface 4.4. Avalon-ST Interface 4.5. Hard IP Status Interface 4.6. Interrupt Interface 4.7. Error Interface 4.8. Hot Plug Interface (RP Only) 4.9. Power Management Interface 4.10. Configuration Output Interface 4.11. Configuration Intercept Interface (EP Only) 4.12. Hard IP Reconfiguration Interface 4.13. PHY Reconfiguration Interface 4.14. Page Request Service (PRS) Interface (EP Only)
4.2. Clocks and Resets x
4.2.1. Interface Clock Signals 4.2.2. Resets
4.2.2. Resets x
4.2.2.1. Interface Reset Signals 4.2.2.2. Function-Level Reset (FLR) Interface (EP Only)
4.4. Avalon-ST Interface x
4.4.1. TLP Header and Data Alignment for the Avalon-ST RX and TX Interfaces 4.4.2. Avalon® -ST RX Interface 4.4.3. Avalon® -ST RX Interface rx_st_ready Behavior 4.4.4. RX Flow Control Interface 4.4.5. Avalon® -ST TX Interface 4.4.6. Avalon® -ST TX Interface tx_st_ready Behavior 4.4.7. TX Flow Control Interface 4.4.8. Tag Allocation
4.4.8. Tag Allocation x
4.4.8.1. Completion Buffer Size
4.6. Interrupt Interface x
4.6.1. Legacy Interrupts 4.6.2. MSI 4.6.3. MSI-X
4.6.3. MSI-X x
4.6.3.1. Implementing MSI-X Interrupts
4.7. Error Interface x
4.7.1. Completion Timeout Interface 4.7.2. VF Error Flags Interface
4.12. Hard IP Reconfiguration Interface x
4.12.1. Address Map for the User Avalon-MM Interface 4.12.2. Configuration Registers Access
4.12.1. Address Map for the User Avalon-MM Interface x
4.12.1.1. User Avalon-MM Control Register (Offset 0x104068)
4.12.2. Configuration Registers Access x
4.12.2.1. Using Direct User Avalon-MM Interface (Byte Access) 4.12.2.2. Using the Debug Register Interface Access (Dword Access)
5. Parameters x
5.1. Top-Level Settings 5.2. Core Parameters
5.2. Core Parameters x
5.2.1. Avalon® Parameters 5.2.2. Base Address Registers 5.2.3. PCI Express and PCI Capabilities Parameters 5.2.4. Device Identification Registers 5.2.5. Configuration, Debug and Extension Options
5.2.3. PCI Express and PCI Capabilities Parameters x
5.2.3.1. Device Capabilities 5.2.3.2. VirtIO Parameters 5.2.3.3. Link Capabilities 5.2.3.4. Legacy Interrupt Pin Register 5.2.3.5. MSI Capabilities 5.2.3.6. MSI-X Capabilities 5.2.3.7. Slot Capabilities 5.2.3.8. Latency Tolerance Reporting (LTR) 5.2.3.9. Process Address Space ID (PASID) 5.2.3.10. Device Serial Number Capability 5.2.3.11. Page Request Service (PRS) 5.2.3.12. Access Control Service (ACS) Capabilities 5.2.3.13. Power Management 5.2.3.14. Vendor Specific Extended Capability (VSEC) Registers 5.2.3.15. TLP Processing Hints (TPH) 5.2.3.16. Address Translation Services (ATS) Capabilities
5.2.3.1. Device Capabilities x
5.2.3.1.1. Multifunction and SR-IOV System Parameters
6. Testbench x
6.1. Endpoint Testbench 6.2. Test Driver Module 6.3. Root Port BFM
6.3. Root Port BFM x
6.3.1. BFM Memory Map 6.3.2. Configuration Space Bus and Device Numbering 6.3.3. Configuration of Root Port and Endpoint 6.3.4. Issuing Read and Write Transactions to the Application Layer 6.3.5. BFM Procedures and Functions
6.3.5. BFM Procedures and Functions x
6.3.5.1. ebfm_barwr Procedure 6.3.5.2. ebfm_barwr_imm Procedure 6.3.5.3. ebfm_barrd_wait Procedure 6.3.5.4. ebfm_barrd_nowt Procedure 6.3.5.5. ebfm_cfgwr_imm_wait Procedure 6.3.5.6. ebfm_cfgwr_imm_nowt Procedure 6.3.5.7. ebfm_cfgrd_wait Procedure 6.3.5.8. ebfm_cfgrd_nowt Procedure 6.3.5.9. BFM Configuration Procedures 6.3.5.10. BFM Shared Memory Access Procedures 6.3.5.11. BFM Log and Message Procedures 6.3.5.12. Verilog HDL Formatting Functions
6.3.5.9. BFM Configuration Procedures x
6.3.5.9.1. ebfm_cfg_rp_ep Procedure 6.3.5.9.2. ebfm_cfg_decode_bar Procedure
6.3.5.10. BFM Shared Memory Access Procedures x
6.3.5.10.1. Shared Memory Constants 6.3.5.10.2. shmem_write Task 6.3.5.10.3. shmem_read Function 6.3.5.10.4. shmem_display Verilog HDL Function 6.3.5.10.5. shmem_fill Procedure 6.3.5.10.6. shmem_chk_ok Function
6.3.5.11. BFM Log and Message Procedures x
6.3.5.11.1. ebfm_display Verilog HDL Function 6.3.5.11.2. ebfm_log_stop_sim Verilog HDL Function 6.3.5.11.3. ebfm_log_set_suppressed_msg_mask Task 6.3.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 6.3.5.11.5. ebfm_log_open Verilog HDL Function 6.3.5.11.6. ebfm_log_close Verilog HDL Function
6.3.5.12. Verilog HDL Formatting Functions x
6.3.5.12.1. himage1 6.3.5.12.2. himage2 6.3.5.12.3. himage4 6.3.5.12.4. himage8 6.3.5.12.5. himage16 6.3.5.12.6. dimage1 6.3.5.12.7. dimage2 6.3.5.12.8. dimage3 6.3.5.12.9. dimage4 6.3.5.12.10. dimage5 6.3.5.12.11. dimage6 6.3.5.12.12. dimage7
7. Troubleshooting/Debugging x
7.1. Hardware 7.2. Debug Toolkit
7.1. Hardware x
7.1.1. Debugging Link Training Issues 7.1.2. Debugging Data Transfer and Performance Issues
7.1.1. Debugging Link Training Issues x
7.1.1.1. Generic Tools and Utilities 7.1.1.2. Signal Tap II Logic Analyzer 7.1.1.3. Additional Debug Tools
7.1.2. Debugging Data Transfer and Performance Issues x
7.1.2.1. Advanced Error Reporting (AER) 7.1.2.2. Second-Level Debug Tools
7.2. Debug Toolkit x
7.2.1. Overview 7.2.2. Enabling the P-Tile Debug Toolkit 7.2.3. Launching the P-Tile Debug Toolkit 7.2.4. Using the P-Tile Debug Toolkit 7.2.5. Using the P-Tile Link Inspector
A. Configuration Space Registers x
A.1. Configuration Space Registers A.2. Configuration Space Registers for Virtualization A.3. Intel-Defined VSEC Capability Registers
A.1. Configuration Space Registers x
A.1.1. Register Access Definitions A.1.2. PCIe Configuration Header Registers A.1.3. PCI Express Capability Structures A.1.4. Physical Layer 16.0 GT/s Extended Capability Structure A.1.5. MSI-X Registers
A.2. Configuration Space Registers for Virtualization x
A.2.1. SR-IOV Virtualization Extended Capabilities Registers Address Map A.2.2. PCIe Configuration Registers for Each Virtual Function
A.2.2. PCIe Configuration Registers for Each Virtual Function x
A.2.2.1. Alternative Routing ID (ARI) Capability Structure A.2.2.2. TLP Processing Hint (TPH) Capability Structure A.2.2.3. Address Translation Services (ATS) Capability Structure A.2.2.4. Access Control Services (ACS) Capability Structure
A.2.2.1. Alternative Routing ID (ARI) Capability Structure x
A.2.2.1.1. ARI Enhanced Capability Header Register (Offset 0x0) A.2.2.1.2. ARI Capability and Control Register (Offset 0x4)
A.2.2.2. TLP Processing Hint (TPH) Capability Structure x
A.2.2.2.1. TPH Requester Enhanced Capability Header (Offset 0x0) A.2.2.2.2. TPH Requester Capability Register (Offset 0x4) A.2.2.2.3. TPH Requester Control Register (Offset 0x8)
A.2.2.3. Address Translation Services (ATS) Capability Structure x
A.2.2.3.1. ATS Enhanced Capability Header (Offset 0x0) A.2.2.3.2. ATS Capability Register and ATS Control Register (Offset 0x4)
A.2.2.4. Access Control Services (ACS) Capability Structure x
A.2.2.4.1. ACS Extended Capability Header (Offset 0x0) A.2.2.4.2. ACS Capability Register (Offset 0x4) A.2.2.4.3. ACS Control Register (Offset 0x6) A.2.2.4.4. Egress Control Vector (Offset 0x8)
A.3. Intel-Defined VSEC Capability Registers x
A.3.1. Intel-Defined VSEC Capability Header (Offset 00h) A.3.2. Intel-Defined Vendor Specific Header (Offset 04h) A.3.3. Intel Marker (Offset 08h) A.3.4. JTAG Silicon ID (Offset 0x0C - 0x18) A.3.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D) A.3.6. General Purpose Control and Status Register (Offset 0x30) A.3.7. Uncorrectable Internal Error Status Register (Offset 0x34) A.3.8. Uncorrectable Internal Error Mask Register (Offset 0x38) A.3.9. Correctable Internal Error Status Register (Offset 0x3C) A.3.10. Correctable Internal Error Mask Register (Offset 0x40)
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
D. Packets Forwarded to the User Application in TLP Bypass Mode x
D.1. EP TLP Bypass Mode (Upstream) D.2. RC TLP Bypass Mode (Downstream)
E. Using the Avery BFM for Intel P-Tile PCI Express Gen4 x16 Simulations x
E.1. Overview E.2. Generate the PCIe PIO Example Design E.3. Integrate Avery BFMs (Root Complex) E.4. Configure the Avery BFM and Update the Simulation Script E.5. Compile and Simulate E.6. View the Results
E.2. Generate the PCIe PIO Example Design x
E.2.1. Avalon® -ST PCIe PIO Example Design
F. Bifurcated Endpoint Support for Independent Warm Resets x
F.1. PCI Express Resets F.2. P-tile PCIe Design Constraints
F.2. P-tile PCIe Design Constraints x
F.2.1. P-tile Dual-Endpoint System Configurations
G. Margin Masks for the P-Tile Avalon Streaming Intel FPGA IP for PCI Express x
G.1. Margin Masks Overview G.2. Nx5 Testing Efficiency G.3. Debug Toolkit Margin Methodology
G.2. Nx5 Testing Efficiency x
G.2.1. First Time Testing G.2.2. Spot Check Testing
G.3. Debug Toolkit Margin Methodology x
G.3.1. Debug Toolkit (DTK) Testing Process G.3.2. DTK Margin Evaluation Based on Margin Mask Values
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express
2. IP Architecture and Functional Description
3. Advanced Features
4. Interfaces
5. Parameters
6. Testbench
7. Troubleshooting/Debugging
8. P-tile Avalon® Streaming Intel FPGA IP for PCI Express* User Guide Archives
9. Document Revision History for the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
A. Configuration Space Registers
B. Root Port Enumeration
C. Implementation of Address Translation Services (ATS) in Endpoint Mode
D. Packets Forwarded to the User Application in TLP Bypass Mode
E. Using the Avery BFM for Intel P-Tile PCI Express Gen4 x16 Simulations
F. Bifurcated Endpoint Support for Independent Warm Resets
G. Margin Masks for the P-Tile Avalon Streaming Intel FPGA IP for PCI Express

9. Document Revision History for the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.10.02 23.3 9.0.3
  • Removed TLP Bypass mode option for all signals in the Completion Timeout Interface section.
  • Added timing waveforms to the Completion Timeout Interface section.
  • Added a Note to the Completion Timeout Interface section stating that the application logic must read the completion timeout interface status register to track the FIFO full and empty markers.
  • Changed the minimum interval time required between a deassertion of pin_perst_n and the next assertion of pin_perst_n from 50us to 500us in the Reset section.
2023.06.26 23.2 9.0.2 Updated the IP version number.
2023.04.03 23.1 9.0.1
  • Updated product family name to "Intel Agilex® 7".
  • Added a clocking requirement to these sections: Interface Clock Signals, Completion Timeout Interface, Hard IP Reconfiguration Interface, and PHY Reconfiguration Interface.
  • Added a clarification on the role of readyAllowance to the sections Avalon® -ST RX Interface rx_st_ready Behavior and Avalon® -ST TX Interface tx_st_ready Behavior.
2023.02.01 22.4 9.0.0 Updated the Function Level Reset (FLR) section to identify the correct PF for the FLR for PF timing diagram.
2022.12.19 22.4 9.0.0
  • Added Device ID settings for Ports 0 and 1 when CvP is enabled to the Top-Level Settings section.
  • Updated the address ranges for the MSI-X Table Offset and PBA Offset in the MSI-X Capabilities section.
  • Added the Appendix chapter Margin Masks for the P-Tile Avalon Streaming Intel FPGA IP for PCI Express.
2022.09.26 22.3 8.3.0
  • Added the Independent PERST section describing how to perform independent reset operations for all active PCIe cores.
  • Added the description for the Clock Source parameter to the Top-Level Settings section.
  • Replaced the Enable RST of PCS & Controller parameter with the Enable Independent Perst parameter in the Top-Level Settings section.
  • Replaced the p<n>_pld_clrpcs_n signals with the p<n>_cold_perst_n_i and p<n>_warm_perst_n_i signals in the Top-Level Settings section.
  • Added the Vendor Specific Extended Capability Offset parameter to the Vendor Specific Extended Capability (VSEC) Registers section.
  • Added a note to the Launching the P-tile Debug Toolkit section clarifying that a full installation of the Intel® Quartus® Prime Pro Edition Software and Devices is necessary to use the Debug Toolkit.
  • Replaced the p<n>_pld_clrpcs_n signals with the p<n>_cold_perst_n_i and p<n>_warm_perst_n_i signals in the P-tile PCIe Design Constraints section.
  • Replaced the p<n>_pld_clrpcs_n signals with the p<n>_cold_perst_n_i and p<n>_warm_perst_n_i signals in the diagrams in the P-tile Dual-Endpoint System Configurations section.
2022.06.20 22.2 8.1.0
  • Added support for the Gen3 1x8 and Gen4 1x8 Endpoint modes.
  • Added the clarification that in 1x8 modes, the x8 port that is active is Port 0.
  • Added the constraint that when two-endpoint configurations are connected to independent hosts, P-tile expects the reference clock for both Port 0 and Port 1 to remain active during warm reset assertions following a global reset.
2022.03.28 22.1 8.0.0
  • Added Riviera* to the list of supported simulators in the Features section.
  • Updated the Overview section of Debug Toolkit to describe the dynamic switching between the User Avalon Memory-mapped Reconfiguration interface and the System Console-based Debug Toolkit when the latter is enabled.
  • Updated the block diagram in the Overview section of Debug Toolkit to show the addition of an arbitration multiplexer inside the P-tile Debug Toolkit module.
2021.12.13 21.4 7.0.0
  • Moved the signal surprise_down_err_o from the Power Management interface to the Hard IP Status interface.
  • Updated Completion buffer size values in the Completion Buffer Size section. Also updated the examples of Completion buffer entries consumed by Memory Read requests. Added a suggested flow diagram that the Application logic can follow to track the Completion buffer entries and schedule NP requests to the IP accordingly.
2021.10.07 21.3 6.0.0
  • Removed the sys_aux_pwr_det_i signal from the Hot Plug Interface. This signal is now in the Power Management Interface.
  • Updated the list of signals in the Power Management Interface section.
  • Updated the timing diagrams in the Configuration Registers Access section.
  • Added the instructions on how to use the Hard IP Reconfiguration Interface to enable and read ECRC and LCRC error event counters to the Additional Debug Tools section.
2021.07.06 21.2 5.0.0
  • Added 450 MHz as the maximum application clock frequency for Gen4 x4 and Gen4 x8 modes for Intel® Stratix® 10 DX devices.
  • Updated the lists of parameters for the TX path and RX path in the Debug Toolkit.
  • Added a note clarifying that RP and TLP Bypass modes are not supported by the Debug Toolkit in this release.
  • Added some signals to the Power Management Interface section: p#_sys_aux_pwr_det_i, apps_ready_entr_l23_i and app_xfer_pending_i.
  • Moved VirtIO parameters under the PCI Express and PCI Capabilities Parameters section.
2021.06.18 21.1 4.0.0
  • Updated the description of how the IP responds to transactions addressed to a function being reset by FLR in the Function Level Reset (FLR) section.
  • Updated the timing diagram in the Hard IP Reconfiguration Interface section.
2021.03.31 21.1 4.0.0
  • Updated the signal descriptions in the Power Management Interface section.
  • Added signals p<n>_cii_vf_num_o[10:0] and p<n>_cii_wr_vf_active_o to the Configuration Intercept Interface (EP Only) section.
  • Updated the description for signal flr_completed_vf_i in the Function-Level Reset (FLR) Interface section.
  • Updated the offsets and address ranges for Table 118 and Table 124 in the Configuration Space Registers Appendix chapter.
  • Added a note in the Top-Level Settings section stating that the independent reset feature will only be supported in a future release of Intel® Quartus® Prime.
2021.02.18 20.4 4.0.0 Replaced pin_perst_n with p<n>_pin_perst_n in the Table in section Signal Tap II Logic Analyzer.
2021.01.19 20.4 4.0.0

Updated the Hard IP Mode options in the Top-Level Settings section.

2020.12.18 20.4 4.0.0

Added Function-Level Reset (FLR) for PF and VF timing diagrams to the Function-Level Reset (FLR) section.

2020.12.14 20.4 4.0.0
  • Added parameters to enable the independent resets for the x8x8 bifurcated mode to the Parameters chapter.
  • Added a note specifying the default value of the Extended Tag field in the Device Capabilities register to the table in the SR-IOV Supported Features List section.
  • Updated the description of the p0_flr_completed_pf_i[7:0] signals in the Function-Level Reset (FLR) Interface (EP Only) section.
  • Updated the table Port Mode Options in TLP Bypass in the Top-Level Settings section to clarify the combinations in which TLP Bypass can be enabled or disabled when multiple ports are available.
  • Updated the directions of signals in the Avalon-ST TX Interface section to match the signal directions in the block symbol.
2020.10.05 20.3 3.1.0
  • Added descriptions for the Device Serial Number tab, the ACS tab to the Parameters chapter.
  • Updated the description of the p0_flr_rcvd_pf_o[7:0] signal bus in the Function-Level Reset (FLR) Interface section.
2020.07.10 20.2 3.0.0
  • Removed configurations that require the Adapter (Gen4 x8 512-bit and Gen4 x4 256-bit) from the Top-Level Settings section because they are not supported in the 20.2 release of Intel® Quartus® Prime.
  • Added description for the Link Inspector in the Debug Toolkit chapter.
  • Added support for the Modelsim simulator to the Features section.
2020.06.22 20.2 3.0.0
  • Added the lane reversal and polarity inversion support to the Features section.
  • Updated the bit ranges for the Next Capability Offset and Version fields in the Intel-Defined VSEC Capability Registers section.
  • Removed the Enable independent pin_perst parameter from the Avalon® Parameters section and the reset pin_perst_2_n from the Interface Reset Signals section. The independent pin_perst option is not supported in the 20.2 release of Intel® Quartus® Prime.
2020.04.30 20.1 2.0.0 Added clarification that VCS is the only simulator supported in the 20.1 release of Intel® Quartus® Prime. Also added a note stating that PIPE mode simulations are not supported in this release.
2020.04.29 20.1 2.0.0 Added notes to the Avalon® -ST RX Interface and Avalon® -ST TX Interface stating that the segmented (split) Avalon® -ST bus interface needs to be leveraged to achieve the expected Gen4 x16 performance.
2020.04.22 20.1 2.0.0
  • Updated the title of the document to P-Tile Avalon® streaming Intel FPGA IP for PCI Express* User Guide to meet new legal naming guidelines.
  • Added new parameters Enable Rx Buffer Limit Ports, P-tile Sim Mode and Enable independent pin_perst.
  • Added diagrams showing examples of buffer limits updates to the RX Flow Control Interface and TX Flow Control Interface sections.
  • Removed Notes stating that data parity is not supported because that feature is available in Intel® Quartus® Prime 20.1.
2020.01.16 19.4 1.1.0
  • Added information about the availability of the CvP Init and CvP Update features in Intel® Stratix® 10 DX and Intel Agilex devices to the Features section.
  • Added the rx_st_tlp_abort_o[1:0] signals to the Avalon® -ST RX Interface section.
  • Removed the app_ready_entr_l23_i signal from the Power Management Interface section.
2019.12.16 19.4 1.1.0
  • Added parameters in Intel® Quartus® Prime to control PASID and LTR.
  • Added MSI extended data support.
2019.11.04 19.3 1.0.0
  • Added resource utilization numbers for the PIO design example in Intel® Stratix® 10 DX devices.
  • Added a step to select Intel® Stratix® 10 DX devices in the Generating the Design Example section.
2019.10.23 19.3 1.0.0
  • Added the description and usage instructions for the P-Tile Debug Toolkit.
  • Added an Appendix chapter on how to use the Avery BFM to run Gen4 x16 simulations.
2019.07.19 19.2 1.0.0 Added features such as SR-IOV support and VirtIO support.
2019.05.03 19.1.1   Initial release.
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