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1.1. Introduction to Custom Platforms
1.2. OpenCL System Architecture
1.3. Hierarchical Structure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform's Hardware
1.4. Intel® Quartus® Prime Software Revisions Describing the Custom Platform
1.5. Intel® FPGA SDK for OpenCL™ and User Environment Setup
1.6. Intel® Arria® 10 Custom Platform Project Setup and Customization Procedure
1.7. Intel® Arria® 10 Custom Platform Customization Example
1.8. Updating Your Custom Platform to Target a Different Device
1.9. Migrating the Custom Platform between Different Intel® Quartus® Prime Software Versions
1.10. Document Revision History for Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL*
1.7.1. Modifying the board.qsys File in the Custom Platform
1.7.2. Modifying the Kernel (freeze_wrapper.v and board_spec.xml)
1.7.3. Updating the Top-Level I/O Ring with the Modified board.qsys and freeze_wrapper.v Files
1.7.4. Updating the Original Custom Platform Directory with the New Custom Platform Modifications
1.7.5. Compilation Log Files
1.7.6. Analyzing the Results from Compilation
1.7.1.1. Opening an Existing Intel® Quartus® Prime Project and the board.qsys Platform Designer System Design
1.7.1.2. Adding the Avalon® -ST Single Clock FIFO Component into the Platform Designer System
1.7.1.3. Connecting the Avalon® -ST Single Clock FIFO Component's Exported Signals in the Top-Level Platform Designer System
1.7.2.1. Opening an Existing Intel® Quartus® Prime Project and the kernel_system.qsys Platform Designer System Design
1.7.2.2. Adding an Avalon® -ST Adapter Component into the Platform Designer System
1.7.2.3. Connecting the Avalon® -ST Adapter Component's Exported Signals in the Top-Level Platform Designer System
1.7.2.4. Modifying the board_spec.xml File
1.7.2.5. Modifying the freeze_wrapper.v File
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1.2. OpenCL System Architecture
An OpenCL System is comprised of a host software and an FPGA board hardware.
Figure 1. Overview of Typical OpenCL Hardware System and Custom Platform
The Host Software box in yellow shows the host application running on the host processor. The FPGA Board Hardware box in grey depicts the hardware accelerator board that the Custom Platform describes.
On the FPGA board hardware side, the Custom Platform provides the post-place-and-route netlist, which includes all of the hardware necessary to communicate with the host and the memory.
The netlist includes DDR memory interfaces, direct memory access (DMA), and any host interface (for example, PCI Express* ( PCIe* )). If there are streaming interfaces to be implemented as channels, these interfaces are also included in the netlist to form an overall communication medium to the host.
When the Intel® FPGA SDK for OpenCL™ Offline Compiler compiles an OpenCL kernel on the FPGA board hardware side, the offline compiler generates a custom data flow circuit representing your kernel and connects the circuit to the Custom Platform hardware.
On the host side, the Custom Platform needs to provide the memory-mapped device (MMD) layer to allow the OpenCL libraries to communicate with your hardware. The SDK user provides the MMD layer in the form of a library. When compiling the host application, the host application links with both the Intel FPGA OpenCL library and the MMD library to create the host executable. The SDK user can then run the host executable, which launches kernels on the FPGA accelerator board.