AN 780: Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL*

ID 683045
Date 10/30/2018
Public

Visible to Intel only — GUID: vpo1478098271770

Ixiasoft

Document Table of Contents

1.7.2.5. Modifying the freeze_wrapper.v File

Create ports on the freeze_wrapper and kernel_system modules for the Avalon® -ST Single Clock FIFO component.
  1. Open the ip/freeze_wrapper.v file in the vector_add directory.
  2. In the freeze_wrapper.v file, create ports on the freeze_wrapper module for the 64-bit Avalon® -ST Single Clock FIFO component.
    input [63:0] board_kernel_sc_fifo_in_data, input board_kernel_sc_fifo_in_valid, output board_kernel_sc_fifo_in_ready, output [63:0] board_kernel_sc_fifo_out_data, output board_kernel_sc_fifo_out_valid, input board_kernel_sc_fifo_out_ready
  3. In the freeze_wrapper.v file, create ports on the kernel_system instance module to match the ports you added in the board_spec.xml file. Connect these signals to the top-level ports of the freeze_wrapper module.
    .kernel_sc_fifo_in_data(board_kernel_sc_fifo_in_data) .kernel_sc_fifo_in_valid(board_kernel_sc_fifo_in_valid), .kernel_sc_fifo_in_ready(board_kernel_sc_fifo_in_ready), .kernel_sc_fifo_out_data(board_kernel_sc_fifo_out_data), .kernel_sc_fifo_out_valid(board_kernel_sc_fifo_out_valid), .kernel_sc_fifo_out_ready(board_kernel_sc_fifo_out_ready)
  4. Save the freeze_wrapper.v file.