AN 780: Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL*

ID 683045
Date 10/30/2018
Public
Document Table of Contents

1.7.1.2. Adding the Avalon® -ST Single Clock FIFO Component into the Platform Designer System

Add an Avalon® -ST Single Clock FIFO component to the board.qsys Platform Designer system.
  1. With board.qsys opened in Platform Designer, add an Avalon® -ST Single Clock FIFO component from the IP catalog. Open the parameter editor and specify the following configuration settings:
    Figure 6. Configuration Settings of the Avalon® -ST Single Clock FIFO Component
  2. Click Finish.
  3. Right-click the board_sc_fifo component at the bottom of the System Contents tab and select Rename.
    Figure 7. Renaming the board_sc_fifo component to kernel_sc_fifo
  4. Change the component’s name to kernel_sc_fifo.
  5. Connect the kernel_sc_fifo component’s clock input interface to the kernel clock by performing the following tasks:
    1. Right-click the clock interface of the kernel_sc_fifo component.
    2. Click Connections > kernel_sc_fifo.clock and then select kernel_clk_gen.kernel_clk.
  6. Connect the reset interface of the kernel_sc_fifo component to the PCIe reset.
    1. Right-click the reset interface of the kernel_sc_fifo component.
    2. Click Connections > kernel_sc_fifo.reset and then select kernel_interface.kernel_reset.
  7. Export the in and out interfaces of the Avalon® -ST Single Clock FIFO component by double-clicking the Export column in the System Contents tab.
    The in and out ports are named kernel_sc_fifo_in and kernel_sc_fifo_out, respectively.
    Figure 8. In and Out Ports of the Avalon® -ST Single Clock FIFO Component
  8. Verify that there are no errors in the message window.