Power Analysis and Optimization FAQ

For Intel® Stratix® 10, Intel Agilex® 7 FPGAs and newer families, the Intel power analysis technology features the Power and Thermal Calculator (PTC) tool, and power analyzer tools in the Intel® Quartus® Prime software. You can download the PTC tool from the FPGA Software Download Center by selecting the latest version of Intel Quartus Prime Pro Software and navigating to the Additional Software tab.

For Intel® Arria® 10 and prior parts, Intel's power analysis technology features Excel-based early power estimators (EPE) and power analyzer tools in the Intel® Quartus® Prime software. You can download the EPE from Intel's website for the specific device family.

The power analyzer is embedded with the Intel Quartus Prime software.

These power analysis tools give you the ability to estimate power consumption from early design concept through design implementation.

For Intel® Stratix® 10, Intel Agilex® 7 FPGAs and newer families, use the PTC to estimate your design's power usage before creating the design or during the design process. You can perform preliminary thermal analysis of your design and plan for power management.

For Intel® Arria® 10 and earlier families, use the EPE to estimate your design's power usage before creating the design or during the design process. You can perform preliminary thermal analysis of your design and plan for power management.

Use the power analyzer tool to obtain an accurate estimation of power after the design is complete, ensuring that thermal and supply budgets are not violated.

The power analyzer provides a flexible framework for specifying signal activities. This reflects the importance of using representative signal activity data during power analysis. Use the following sources to provide information about signal activity:

• Simulation results
• User-entered node, entity, and clock assignments
• User-entered default toggle rate assignment
• Vectorless estimation

The power analyzer also lets you mix and match the signal activity data sources on a signal-by-signal basis.

The accuracy of power estimation depends on the stage of the design. For a partially completed design or in the concept phase, use the PTC or EPE (as applicable) to obtain an initial power estimate. For designs that are completed, simulation-based power estimation generated from the power analyzer provides an accurate power estimation compared to early power estimates.

For Intel® Stratix® 10, Agilex and newer, the accuracy of the power model is determined on a per-power-rail basis for the Intel Quartus Prime Power Analyzer.

For most Intel® Stratix® 10 designs, the Intel Quartus Prime Power Analyzer has the following accuracy, assuming final power models: Within 10% of silicon for the majority of power rails with higher power, assuming accurate inputs and toggle rates.

For most Intel Agilex designs, the Intel Quartus Prime Power Analyzer has the following accuracy, assuming final power models: Within 10% of silicon for all power rails, assuming accurate inputs and toggle rates.

For Intel® Arria® 10 and before, the power analyzer tool is accurate (to within ±20%) of actual device power consumption, provided that supplied input vectors are representative of typical design operation. The accuracy of the results of the early power estimator is generally within ±20% of the power analyzer estimates, assuming perfect toggle-rate entry.

Yes. The simulation-based power analyzer is more accurate because it uses design details such as routing, placement, and simulation results to improve the accuracy.

Signal activity and static probability information may be derived from a Value Change Dump File (.vcd) generated by the EDA simulators.

Refer to chapter 2.3.2.1. Using Simulation Signal Activity Data in Power Analysis of the Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization, for information on how to generate .vcd file.

Intel Quartus Prime software offers power-driven compilation to fully optimize device power consumption. Power-driven compilation focuses on reducing your design’s total power consumption using power-driven synthesis and power-driven place-and-route.

For additional information on different power optimization techniques, refer to the Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

Programmable power technology allows you to program the core logic in Stratix® III and Stratix® IV FPGAs for high speed or low power, depending on design requirements. Programmable Power Technology enables Stratix III and Stratix IV FPGAs to deliver the lowest power and the highest performance.

For example, to set an NMOS transistor in the core of Stratix IV FPGAs to:

• Low-power mode, the Intel Quartus Prime software reduces the back bias voltage (making it more negative), which makes the transistor harder to turn on. This reduces the leakage current and saves power.
• High-performance mode, the Intel Quartus Prime software increases the back bias voltage (making it less negative), which makes the transistor easier to turn on in the few timing-critical paths to help meet the design's specified timing constraints and deliver the maximum performance.

The Intel Quartus Prime software automatically controls which logic operates in high-speed mode and which operates in low-power mode, based on the timing constraints specified for the design.

For additional information on programmable power technology, refer to the 40 nm power management and advantages white paper.

Refer to the "Report Worksheet" section in the Early Power Estimator User Guide

Power supply estimations for each device density and package combination are in the "Report" tab of the PTC/EPE. Use "maximum" power characteristics to see the worst case static or standby power specification.