Founded in 1993, CAST continues to thrive as the longest-running — and most experienced — independent IP supplier. Our mission has been to provide proven, low-risk IP cores, under simple and flexible licensing terms, coupled with outstanding support. The years of work we have done to perfect IP reuse, improve IP quality standards, and refine sales and business practices yield a product line and a partner network that offer you a better IP experience, today and in the future. Proven, Low-Risk IP: Our goal is to maximize IP benefits for our customers by delivering high-quality, easy-to-use, cost-effective solutions to real system development challenges. CAST quality standards are high, and all our IP undergoes rigorous verification and testing before it gets to you. We use industry-standard verification methodologies, develop and test prototypes, participate in industry collaboration plugfests, and more to ensure proper functioning and smooth integration. Our practices have been extensively tested and proven, as we have helped thousands of customers ship billions of units in hundreds of application areas. Simple, Flexible Licensing: We help you get to work quickly, with fine-tuned project options and licensing terms that ensure smooth legal sign-off. Most CAST IP is available royalty-free, and is extremely cost-effective. Outstanding Support: CAST IP comes with some of the best customer support in the industry. Our goal is to help make you successful, not just sell you IP, and we have the experience and resources to make that happen.
Offerings
Offering
This JPEG-D-S core is a high-performance JPEG decoder supporting the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard. It is suitable for decompressing JPEG images and the video payload of Motion-JPEG container formats.. The core decodes one color sample per clock cycle, and is able to process Full-HD 1080p video in most FPGA devices. Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. SoC integration is straightforward thanks to standardized AMBA' interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access. FEATURES: Area-efficient, high-performance Baseline JPEG decoder for ASIC and FPGA Standards Support ISO/IEC 10918-1 Standard Baseline Decoder Single-frame JPEG images and Motion JPEG payloads Up to four color components 8-bit color samples All widely used color subsampling formats, and any image size up to 64k x 64k All scan configurations and all JPEG formats All marker segments expect DNL Up to four Huffman Tables Up to four 8-bit or 16-bit Quantization tables Interfaces AXI Streaming I/O data interfaces APB Control/Status interface Optional AHB wrapper with DMA capabilities Performance and Size One decoded sample per clock cycle Small silicon footprint (65k Gates) Ease of Integration Requires no programming or control from host Reports image format Detects and reports marker syntax errors Delivered with bit-accurate software model Optional Block-to-Raster Conversion with AXI or standard memory interface towards the lines buffer Format Available as a netlist for ASICs or FPGAs
Offering
The CAN-CTRL is a CAN bus controller that performs serial communication according to the CAN 2.0, CAN FD, and CAN XL specifications. The CAN core is easy to use and integrate, featuring programmable interrupts, data and baud rates; and a configurable number of independently programmable acceptance filters. It implements a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application. The number of receive buffers is synthesis-time configurable. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). An optional wrapper instantiating multiple CAN controller cores eases integration in cases where multiple bus nodes need to be controlled by the same host processor. Finally, the CAN-CTRL provides error analysis, diagnosis, maintenance, and optimization features. The CAN bus controller comes in three variants: 2.0, FD, and XL. The 2.0 variant supports only the CAN 2.0 specification, the FD variant adds support for CAN FD, and the XL variant supports the CAN 2.0, CAN FD, and CAN XL standards. Each of the three core variants is available in two versions: Standard and safety-enhanced. The safety-enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The safety-enhanced versions are certified as ISO-26262 ASIL-D ready. The CAN-CTRL is extensively verified, and proven in several plug fests and a large number of production designs.
Offering
This IP core supports the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-performance, hardware JPEG encoder with very low processing latency. The JPEG-E-S Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with 8-bit color samples and up to four color components, in all widely-used color subsampling formats. The encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG encoders available, it synthesizes to about 3,500 ALMs. The core operates without any assistance from the host processors, and uses AXI-stream interfaces for pixel and stream data, and a 32-bit APB slave interface for registers access. FEATURES: Performs Baseline Sequential DCT JPEG encoding of images or video for ASICs or FPGAs, with small silicon area, high performance, and low latency. Standards Support ISO/IEC 10918-1 Standard Baseline Sequential DCT mode Encodes single-frame JPEG images and Motion JPEG payloads 8-bit per color samples Up to four color components; any image size up to 64k x 64k Handles all scan configurations and all JPEG formats APP, COM, and restart markers Programmable Huffman and Quantization tables Rate Control Options Image: Limits the size of each individual frame Video: Regulates bit rate over a number of input frames Interfaces AXI Streaming I/O data interfaces APB Control/Status interface Optional AHB wrapper with DMA capabilities Performance and Size One encoded sample per clock cycle Small silicon footprint (about 70k ASIC gates) Ease of Integration Automatic program-once/encode-many operation Simple, dedicated timestamps interface Included bit-accurate software model generates test vectors, expected results, and core programming values Optional Raster-to-Block Conversion with AXI or standard memory interface to the lines buffer Format Available as a netlist for ASICs or FPGAs
Offering
The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (264 – 1) bits. Developed for easy reuse in ASIC and FPGA applications, the SHA-256 is available optimized for several technologies with competitive utilization and performance characteristics. Support for the AMBA bus interface is available as an option. The SHA-256 core has been robustly verified and is silicon-proven. FEATURES: Designed according to the FIPS 180-2 StandardNIST Certified Maximum message length up to (264 – 1) bits Suitable for data authentication application Simple, fully synchronous, reusable design Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices Complete deliverables include test benches, C model and test vector generator
Offering
The core is a UDP/IP hardware protocol stack. Designed for standalone operation, the core offloads the host processor from the task of UDP/IP encapsulation and enables media streaming with speeds up to 1Gbps even in processor-less designs. Trouble-free operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core implements the ARP Protocol, which is critical for multiple access networks, and the Echo Request and Reply Messages of the ICMP widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a DHCP server. Finally, the core supports 801.1Q tagging, and is suitable for operation in a Virtual LAN. The core is easy to integrate in systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces, or via registers. FEATURES: Complete UDP/IP Hardware Stack10/100/1000 Mbps Ethernet with a 31.25 MHz clock10Gbps Ethernet with a 312.5 MHz clock IPv4 support without packet fragmentation Jumbo and Super Jumbo Frames Transmit and Receive ARP with Cache ICMP (Ping Reply)IGMPv3 (Multicast)UDP/IP Unicast and Multicast UDP Port Filtering UDP/IP Checksums generation and validation, and optional Ethernet CRC validation VLAN (IEEE 802.1Q) support1 to 32 UDP transmit. and 1 to 32 UDP receive channels Ethernet Framing processing for non-UDP user-provided packets Optional DHCP client Trouble-Free Operation Run time programmable network parameters Local MAC address, Local IP address, Gateway IP address, and IP subnet mask Per-channel: Destination IP address, Source. and Destination UDP ports, multicast enable/disable and receive group ARP support for operation in networks with Dynamic IP allocation Easy SoC Integration Flexible interfaces: Packet Data: 32-bit streaming-capable Avalon®-ST or AXI4-StreamControl/Status Registers: Generic 32-bit SRAM-like, or optionally 32-bit AHB, AXI, Avalon®-MM or Wishbone Separate clock domains for packet processing and control/status interfaces Configurable buffer sizes Rich interrupt support for system events Optionally available pre-integrated with: Intel®, or other third-party eMAC core CAST Image and Video compression cores
Offering
The core is a UDP/IP hardware protocol stack. Designed for standalone operation, the core offloads the host processor from the task of UDP/IP encapsulation and enables media streaming with speeds up to 50Gbps even in processor-less designs. Trouble-free operation is ensured through run-time programmability of all the required network parameters (local, destination, and gateway IP addresses; UDP ports; and MAC address). The core implements the ARP Protocol, which is critical for multiple access networks, and the Echo-Request and Reply Messages of the ICMP are widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a DHCP server. Finally, the core supports 801.1Q tagging and is suitable for operation in a Virtual LAN. The core is easy to integrate into systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces, or via registers mapped on an SoC bus.
Offering
The core is a UDP/IP hardware protocol stack. Designed for standalone operation, the core offloads the host processor from the task of UDP/IP encapsulation and enables media streaming with speeds up to 25Gbps even in processor-less designs. Trouble-free operation is ensured through run-time programmability of all the required network parameters (local, destination, and gateway IP addresses; UDP ports; and MAC address). The core implements the ARP Protocol, which is critical for multiple access networks, and the Echo-Request and Reply Messages of the ICMP are widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a DHCP server. Finally, the core supports 801.1Q tagging and is suitable for operation in a Virtual LAN. The core is easy to integrate into systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces, or via registers mapped on an SoC bus.
Offering
The UDPIP-100G is a 100Gbps UDP/IP hardware protocol stack. Designed for standalone operation, the core offloads the host processor from the task of UDP/IP encapsulation and enables communication with speeds up to 100Gbps even in processor-less designs. Trouble-free operation is ensured through run-time programmability of all the required network parameters (local, destination, and gateway IP addresses; UDP ports; and MAC address). The core can use a static IP address or automatically request and acquire an IP address from a DHCP server. It also supports ARP, ICMP, IGMPv3, and VLAN (801.1Q tagging) without requiring any software assistance. The core is easy to integrate into systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces (up to 32 for Rx data and up to 32 for Tx Data), or via registers mapped on an SoC bus.
Offering
The TCPIP-1G/10G core implements a complete TCP/IP Hardware Protocol Stack. The core acts either as a server or a client and without any assistance from the host autonomously system, opens, maintains, and closes TCP connections. The system integrating the TCPIP-1G/10G core can configure network parameters and preferences by accessing its control registers, and the core is then able to receive and send data via streaming data interfaces. The core is highly configurable. The maximum number of simultaneous TCP sessions is configurable; it can be as high as 32,768 for devices like data servers, or as small as 1 for simpler edge devices. Further options include implementing a DHCP client, enabling or disabling the reassembly of out-of-order TCP packets data, and integrating a UDP hardware stack. Finally, users can choose the packet processing mode, either cut-through or store-and-forward. In cut-through mode, the payload data are delivered to the host system as they arrive without any internal packet buffering and before the packets’ integrity can be validated. As a result, the core operating in cut-through mode features extremely low latency and requires less memory, but it cannot reassemble out-of-order packets and may deliver data that will subsequently be marked as corrupted. Under the store-and-forward mode of operation, the core will always deliver verified, in-order packets but it will have higher latency and require more memory resources.
Offering
LZ4SNP-D is a custom hardware implementation of a lossless data decompression engine for the LZ4 and Snappy compression algorithms. The core receives compressed files, automatically detects the LZ4 or Snappy format, and outputs the decompressed data. The core features fast processing with low latency and high throughput. In its default configuration, LZ4SNP-D outputs 7.8 bytes of decompressed data per clock cycle and can be clocked at frequencies exceeding 250MHz on Intel® Arria® 10 devices. Designers can scale the throughput by instantiating the core multiple times to achieve throughput rates exceeding 100Gbps. The processing latency is approximately 30 clock cycles.The decompression core operates on a standalone basis—offloading the host CPU from the demanding task of data decompression—and has been designed for easy integration and use. No preprocessing of the incoming compressed files is required, as the core parses the file headers, checks the input files for errors, and outputs the decompressed data payload. Extensive error tracking and reporting enable the core to ensure smooth system operation and error recovery, even in the presence of errors in the compressed input files. Furthermore, internal memories can optionally support Error Correction Codes (ECC) to simplify achieving enterprise-class reliability or functional safety requirements.
Offering
The I3C-SC core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Secondary Controller core compliant with the latest MIPI I3C Basic specification. As a secondary controller, the I3C-SC can act either as a bus target or a bus controller. Compliant to the I3C Basic specification, the core communicates in Single Data Rate (SDR) mode but can tolerate High Data Rate (HDR) traffic. It can coexist and communicate with legacy I2C devices, and it can optionally be configured to operate as such in an I3C or I2C bus. When acting as a target, the I3C-SC needs no firmware support to parse and execute the broadcast or direct Common Command Codes (CCCs) relevant to I3C Basic targets. It can be assigned a Dynamic Address by the bus controller or use its legacy I2C static address, it supports Hot-Join and can generate In-Band Interrupts when directed by the host to do so. When the I3C-SC core is the only bus controller, then Hot-Join is not possible, and static addressing should be used. Designed for easy integration, the I3C-SC can operate in two different modes. Under normal mode, data from private I3C or legacy I2C write transfers are stored to a FIFO and made available to the host via an APB Subordinate interface. In a similar way, the host provides data to be used for private I3C or legacy I2C read transfers via the core’s APB subordinate interface. Alternatively, the core can operate in I3C-to-AHB bridging mode, where it autonomously converts private I3C or legacy I2C transfers to accesses on its AHB manager port using a simple yet configurable over-I3C protocol. Under the I3C-to-AHB bridging mode, the core acts as an I3C bus target, needs no software assistance, and provides the I3C bus controller access to the local AHB bus, enabling remote monitoring, configuration, debug, or data exchange. The selection between normal and bridging operation modes is under software control via the core’s control register.
Offering
The I2S-TDM IP core is a highly configurable, full-duplex, multichannel serial audio transceiver. The transceiver can act as a controller (master) or a target (slave) for Inter-IC Sound (I2S) and Time-Division Multiplexed (TDM) audio interfaces, exchanging multi-channel audio samples over a configurable number of serial lines (pins).The I2S-TDM offers a number of configuration options to satisfy a wide range of serial audio interface requirements. The operation mode (controller or target), sample width, sample rate, frame format, number of channels and their allocation to physical lines are all programmable at run time. At synthesis time, designers can choose the maximum number of audio channels and serial data lines the transceiver can support. The core is designed for ease of use and integration and adheres to the industry’s best coding and verification practices. The core’s control and status registers (CSR) are accessed through a 32-bit AMBA® APB interface, or, optionally, an AXI4 Lite inter-face. The host system exchanges audio data with the core either via this CSR interface or via dedicated AXI4-Stream interfaces. The system interfaces operate with a clock that is independent from the audio master and serial bit clocks, and the core implements clean clock domain crossing boundaries.
Offering
The PNG-E core implements a lossless image compression engine compliant with the Portable Network Graphics (PNG) file format specified in the ISO/IEC 15948 and RFC 2083 standards. The encoder core can compress greyscale or color (RGB) images, with 8 and 16 bits per color, with or without alpha transparency, and produces complete PNG files. It exhibits excellent compression efficiency thanks to its ability to automatically and dynamically choose the optimal prediction filter per line. It supports all four prediction filters, LZ77 with a configurable history window, and static huffman tables, and computes CRC and Adler32 checksums as provisioned by the standard. The core does not currently support the interlaced mode, dynamic huffman tables, and images with less than 8 bits per color, but these can be added on request. The easy-to-use PNG-E core interfaces to the system via standardized AMBA® interfaces: it accepts images and outputs compressed data via AXI4-Stream interfaces and provides access to its control and status registers via a 32-bit APB interface. After its registers are programmed with the image dimensions and color format, the core can encode an arbitrary number of images without requiring any assistance or action from the system. The core provides one interrupt signal per direction to facilitate integration with a DMA engine. These interrupts are asserted when the input or output FIFO occupancy reaches a run-time programmable threshold.
Offering
The L8051XC1 core implements an MCS 51-compatible microcontroller that is specially designed to match the timing and peripherals of legacy 8051 MCU based systems. The core can be configured to execute an instruction every 12, 6, or 4 clock cycles. Architectural extensions are user-selectable, including multiple data-pointers, a multiply-division unit, and a power management unit. Furthermore, the 8051 CPU can be coupled with a wide range of peripherals matching the behavior and timing of peripherals found in legacy architectures from various vendors. Several pre-configured versions are offered; custom variations are also available.
Offering
ZipAccel-D is a custom hardware implementation of a lossless data decompression engine that complies with the Inflate/Deflate, GZIP/GUNZIP, and ZLIB compression standards. The core features fast processing, with low latency and high throughput. On average the core outputs three bytes of decompressed data per clock cycle, providing over 3Gbps in most Intel® FPGA devices. Designers can scale the throughput further by instantiating the core multiple times to achieve throughput rates exceeding 100Gbps. The latency is in the order of a few tens of clock cycles for blocks coded with static Huffman tables, and typically less than 2,000 cycles for blocks encoded with dynamic Huffman tables. The decompression core has been designed for ease of use and integration. It operates on a standalone basis, off-loading the host CPU from the demanding task of data decompression. The core receives compressed input files and outputs decompressed files. No preprocessing of the compressed files is required, as the core parses the file headers, checks the input files for errors, and outputs the decompressed data payload. Featuring extensive error tracking and reporting errors, the core enables smooth system operation and error recovery, even in the presence of errors in the compressed input files. Furthermore, internal memories can optionally support Error Correction Codes (ECC) to simplify the achievement of Enterprise-Class reliability or functional safety requirements. The ZipAccel-D core is a microcode-free design developed for reuse in ASIC and FPGA implementations. Streaming data, optionally bridged to AMBA AXI4-stream, interfaces ease SoC integration. Technology mapping is straightforward, as the design is scan-ready, LINT-clean, microcode-free, and uses easily replaceable, generic memory models.
Offering
The H264-D-BP IP core is a video decoder complying with the Constrained Baseline Profile of the AVC/H.264 standard. It implements a hardware decoder with very low latency and high throughput that is suitable for live streaming and other delay-sensitive applications up to full HD resolution. The decoder adds just one macroblock line of latency, which means a negligible real-world latency under one msec for most widely used video formats, including HD/720p and Full-HD/1080p video. The H264-D-BP is designed for trouble-free SoC integration. It operates on a stand-alone basis such that decoding proceeds with no assistance or input from the host processor. The decoder's memory interface is extremely flexible: it operates on a separate clock domain, is independent of the external memory type, and is tolerant to large latencies. The decoder reports decompressed video parameters, detects and reports bitstream errors to the system, and simplifies video cropping at its output.
Offering
The PCI-T32MF implements a target-only PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz (PCI clock). The core offers one to eight independent PCI functions in a single chip, each implementing 64 to 256 bytes of PCI Configuration Space registers as required. Each function supports up to six Base Address Registers, with both I/O and Memory space decoding from 16 bytes up to 4GB.
Offering
This video encoder supports the Constrained Baseline Profile of the H.264 standard It implements an ultra-high throughput, UHD- capable hardware encoder that is optimized for ultra-low-latency video streaming at low bit rates. The H264-E-BPF requires significantly less FPGA resources than most equally capable H.264 cores allowing for cost-effective FPGA implementations. Its small silicon footprint, low memory bandwidth, and zero software overhead enable H.264 coding at an extremely low energy cost. Depending on its configuration the core is able to process Full-HD or UHD/4K video on Intel® FPGAs. The core produces high-quality video, even at low bit-rates, and features extremely low latency. It uses a constant Qp to output VBR streams, or automatically regulates Qp to output CBR streams. In CBR mode it responds rapidly to video content changes. This can be combined with Intra-Refresh coding to effectively eliminate bit-rate peaks, while preserving the periodic intra-coded references.
Offering
This IP core supports the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, hardware JPEG encoder that can compress high pixel rate video using significantly fewer silicon resources and less power than encoders for video compression standards such as HEVC/H,265, DSC, AVC/H.264, or JPEG200. The JPEG-EX-F Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with up to 12-bits per color samples and up to four color components, in all widely-used color subsampling formats. Depending on its configuration, the encoder processes from 2 to 32 color samples per clock cycle, enabling it to compress UHD (4K/8K) video and/or very high frame video. The core operates without any assistance from the host processors, and uses AXI-stream interfaces for pixel and stream data, and a 32-bit APB slave interface for registers access.
Offering
The PCI-M32MF implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz (66 MHz optional) PCI clock. The core offers one to eight independent PCI functions in a single chip, each implementing 64 to 256 bytes of PCI Configuration Space registers as required. Each function supports up to six Base Address Registers, with both I/O and Memory space decoding from 16 bytes up to 4GB.
Offering
The JPEG-LS-D core implements a lossless and near-lossless image decompression engine that is compliant with the JPEG-LS, ISO/IEC 14495-1 standard. The decoder core can decompress any JPEG-LS stream or JPEG-LS payload of image container formats, such as DICOM. It accepts compressed streams of images with up to 16-bit per color samples and up to four color components, in all widely used color subsampling formats. Supporting oversize image dimension parameters, the core can decode images with resolutions exceeding 64k x 64k pixels. The easy-to-use JPEG-LS-D core operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The core accepts compressed data and outputs pixel data and passes metadata to the system via AXI4-Stream interfaces, and it provides access to its control and status registers via a 32-bit APB interface. A wrapper that bridges the AXI-Stream interfaces to AXI4 can optionally be delivered with the core.
Offering
The main PCI-M32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on the application development. The PCI-M32 Interface supports 32-bit address/data bus and operates up to 33 MHz (66 MHz optional) PCI clock frequency. It is fully compliant with the PCI Local Bus Specification, Revision 2.3. The PCI-M32 Interface has both Master and Target capabilities. The interface implements 64 bytes of PCI Configuration Space registers. It is possible to extend the Configuration Space up to 256 bytes if required. The Target part supports up to six Base Address Registers with both I/O and Memory space decoding from 16 bytes up to 2 GB. Both Target and Master supported commands are: - Configuration Read, Configuration Write - Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read Line (MRL) - I/O Read, I/O Write
Offering
Overview The HSDLC core is a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols. The core operates as a peripheral to a host processor and is easy to integrate with both modern and legacy processors. Control and status registers are accessible via an APB or a generic 80c51-like bus interface, and a comprehensive set of interrupt signals facilitates interrupt-based operation. The controller’s great flexibility enables a variety of serial link setups. It provides two independent interfaces, one for transmitting and one for receiving data. Both interfaces provide control signals for the link drivers to support both full- and half-duplex operation. The controller can be programmed to use hardware flow control signals (RTS/CTS) and it can also detect collisions. The baud-rate is programmable and limited only by the link drivers and the core’s clock frequency. The core derives the receive clock from the received serial data, or uses an externally provided receive clock. The HSDLC is available in two versions: Normal, and Safety-Enhanced. The Safety-Enhanced version implements triple-modular redundancy (TMR) to provide full immunity to single-bit upsets and errors and complies to Design Assurance, Level A (DAL-A) of the DO-254 standard.
Offering
ZipAccel-C is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards. The core receives uncompressed input files and produces compressed files. No post-processing of the compressed files is required, as the core encapsulates the compressed data payload with the proper headers and footers. Input files can be segmented, and segments from different files can be interleaved at the core’s input. The core’s flexible architecture enables fine-tuning of its compression efficiency, throughput, and latency to match the requirements of the end application. Throughputs in excess of 100 Gbps are feasible in FPGAs, and latency can be as small as a few tens of clock cycles. ZipAccel-C offers compression efficiency practically equivalent to today’s popular deflate-based software applications. Analyzing processing speed versus compression efficiency to achieve the best tradeoff for a specific system is facilitated by the included software model, and by support from our team of data compression experts. ZipAccel-C has been designed for ease of use and integration. It operates on a standalone basis, off-loading the host CPU from the demanding task of data compression, and optionally from the task of encrypting the compressed stream. Streaming AXI-Stream or native FIFO-like data interfaces ease SoC integration. Technology mapping is straightforward, as the design is scan-ready, LINT-clean, microcode-free, and uses easily replaceable, generic memory models. Memory blocks can optionally support Error Correction Codes (ECC) to simplify the achievement of Enterprise-Class reliability requirements. Furthermore, input file segmentation can limit the inter-file latency and helps users achieve Quality of Service (QoS) objectives.
Offering
The TSN-SE implements a switched endpoint controller suitable for the implementation of endpoints in-daisy-chained Time Sensitive Networking (TSN) Ethernet networks. It integrates hardware stacks for timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav, IEEE 802.1Qbv), frame preemption (IEEE 802.1Qbu, IEEE 802.1Qbr), and a low-latency Ethernet MAC. The controller core is designed to enable high-precision timing synchronization, flexible yet accurate traffic scheduling and extremely low latency switching.
Offering
This IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-performance, hardware JPEG encoder with very low processing latency. The JPEG-EX-S Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. The encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG encoders available, it synthesizes to about 4,000 ALMs. The core operates without any assistance from the host processors, and uses AXI-stream interfaces for pixel and stream data, and a 32-bit APB slave interface for registers access. FEATURES: Performs Baseline and Extended Sequential DCT JPEG encoding of images or video for ASICs or FPGAs, with small silicon area, high performance, and low latency. Standards Support ISO/IEC 10918-1 Standard Baseline and Extended Sequential DCT modes Single-frame JPEG images and Motion JPEG payloads 8-bit and 12-bit per color samples Up to four color components; any image size up to 64k x 64k All scan configurations and all JPEG formats APP, COM, and restart markers Programmable Huffman and Quantization tables Rate Control Options Image: Limits the size of each individual frame Video: Regulates bit rate over a number of input frames. Interfaces AXI Streaming I/O data interfaces APB Control/Status interface Performance and Size One encoded sample per clock cycle Small silicon footprint (about 80k ASIC gates) Ease of Integration Automatic program-once/encode-many operation Simple, dedicated timestamps interface Included bit-accurate software model generates test vectors, expected results, and core programming values Optional Raster-to-Block Conversion with AXI or standard memory interface to the lines buffer
Offering
This JPEG-DX-F core is an ultra-high-performance JPEG decoder supporting the Baseline and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It is suitable for decompressing JPEG images and the video payload of Motion-JPEG container formats. Depending on its configuration, the core decodes from 2 to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-EX-F Encoder Core. This Encoder-Decoder pair provides an extremely cost-effective solution for streaming or archiving UHD video, or very high frame rates at lower resolutions. Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. SoC integration is straightforward thanks to standardized AMBA interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access.
Offering
This is a video encoder supporting the Constrained Baseline Profile of the H.264 standard It Implements an energy-efficient hardware architecture that is optimized for ultra-low-latency video streaming at low bit rates. The H264-E-BPS requires less than half the silicon area of most competing encoder cores under 9k ALMs allowing for cost-effective FPGA implementations. Its small silicon footprint, low memory bandwidth, and zero software overhead enable H.264 coding at an extremely low energy cost. The core is able to process Full-HD video on most Intel® FPGAs. Despite being small, the core produces high quality video, even at low bit-rates, and features extremely low latency. It uses a constant Qp to output VBR streams, or automatically regulates Qp to output CBR streams. In CBR mode it responds rapidly to video content changes. This can be combined with Intra-Refresh coding to effectively eliminate bit-rate peaks, while preserving the periodic intra-coded references.
Offering
The H16550S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16550 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices. The H16550S can be run in either 16450- compatible character mode or in 16550- compatible FIFO mode, where an internal FIFO relieves the CPU of excessive software overhead. The H16550S core can be utilized for many communication applications including: Serial or modem computer interface, or serial interface within modems and other devices
Offering
The TSN-SW implements a highly flexible, low-latency, multiport TSN Ethernet switch. It supports Ethernet bridging according to the IEEE 802.1Q-2018 standard and implements the essential TSN timing synchronization and traffic-shaping protocols (i.e. IEEE 802.1as, 802.1Qav, 802.1Qbv, 802.1Qbu, 802.1br and optionally 802.1Qci, and 802.1CB). Featuring a configurable number of ports, the Layer-2 switch operates in cut-through mode at wire speed and can provide sub-microsecond port-to-port latency. The core is hence suitable for applications with demanding real-time requirements. The TSN-SW operates efficiently under different usage scenarios and is highly configurable. Users can configure key factors via the core’s control registers: the mapping of VLAN priority levels to TSN traffic classes, the traffic scheduling and preemption parameters, the treatment of special frames (i.e. broadcast, unknown, & internal), as well as the VLAN ID and MAC lookup tables used for frame forwarding and filtering. The host system can also switch the mode of operation of each individual port from cut-through to store-and-forward to eliminate the propagation of bad frames at the cost of increased latency. The core otherwise operates autonomously and only requires software assistance at runtime for correct time synchronization; a lightweight ptp/802.1AS software stack comes with the core for that purpose. The TSN-SW uses standard AMBA® interfaces to ease integration. Its control and status registers are accessible via a 32-bit-wide APB bus, and packet data can be exchanged with the host system via AXI-Streaming interfaces with 32-bit data buses. The TSN-SW is designed with industry best practices and is available in synthesizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample synthesis and simulation scripts, an extensive testbench, and comprehensive documentation.
Offering
The CSENT core implements a controller for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and also the industry de-facto standard Short PWM Code (SPC) protocol, and can be used for conveying data from one or multiple sensors to a centralized controller using a single SENT line. The CSENT core can be configured as a Transmitter and/or as a Receiver, and therefore it is suitable for adding a SENT interface to devices transmitting sensor data or to controllers receiving sensor data. It provides access to its control, status, and data registers via a 32-bit APB bus interface, and a comprehensive set of interrupt signals facilitates interrupt-based operation. The core allows for Transmitter operation without requiring any external programming or control. The reset values for all its control registers are defined at synthesis time, and at run time the system only needs to write sensor data to the core.
Offering
The LIN core is a communication controller that transmits and receives complete LIN frames to perform serial communication according to the LIN Protocol Specification. The LIN controller can be implemented as a master or as a slave and operate on LIN 1.3, 2.0, 2.1 or 2.2 LIN network. It uses a single master/multiple slave concept for message transfer between nodes of the LIN network. The message transfer can be controlled via a microcontroller interface and a LIN transceiver is needed for the connection to the LIN bus. The LIN core is available in two versions: Standard and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The Safety-Enhanced versions are certified as ISO- 26262 ASIL-D Ready. The robustly verified core has been production-proven multiple times.
Offering
The AES-GCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Four architectural versions are available to suit system requirements. The Standard version (AES-GCM-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-GCM-F) achieves higher throughput using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block depending on key size. For applications where throughput is critical there are two additional versions. The High Throughput AES-GCM-X can process 128 bits/cycle and the Higher Throughput AES-GCM-X2 can process 256 bits/cycle respectively independent of the key size. GCM stands for Galois Counter. GCM is a generic authenticate-and-encrypt block cipher mode. A Galois Field (GF) multiplier/accumulator is utilized to generate an authentication tag while CTR (Counter) mode is used to encrypt. The AES-GCM cores are robustly verified and proven in numerous shipping products.
Offering
The AES-XTS encryption IP core implements hardware encryption/decryption for sector-based storage data. It uses the AES block cipher, in compliance with the NIST Advanced Encryption Standard, as a subroutine. The core processes 128 bits per cycle, and is programmable for 128- and 256-bit key lengths. Two architectural versions are available to suit system size and throughput requirements. The High Throughput XTS-X is more compact and can process 128 bits/cycle independent of the key size. The Higher Throughput XTS-X2 can process 256 bits/cycle independent of the key size. Both versions have a 128-bit data path. The AES-XTS cores are robustly verified and proven in numerous shipping products.
Offering
The AES-P encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-P-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-P-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. It can be programmed to use any of the following cipher modes: CBC, CTR, ECB, and OFB. The core works with a pre-expanded key, or with optional key expansion logic. The AES-P core is robustly verified and proven in numerous shipping products.
Offering
The AES-CCM encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-CCM-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-CCM-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. CCM stands for Counter with CBC-MAC mode. CCM is a generic authenticate-and-encrypt block cipher mode. CBC-MAC is utilized to generate an authentication string while CTR mode is used to encrypt. The AES-CCM cores are robustly verified and proven in numerous shipping products.
Offering
The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying with the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS) and traffic shaping (IEEE 802.1Qav and 802.1Qbv), and a low-latency Ethernet MAC. The controller core is designed to enable high-precision timing synchronization and flexible yet accurate traffic scheduling. Requiring minimal software assistance for its initialization, it features extremely low and deterministic ingress and egress latencies, and simplifies the development of time-aware applications. While operating autonomously, the TSN_EP provides the system with timing information (time-stamps, alarms, etc.) that is typically required for the operation of a TSN network bridge or endpoint. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application's requirements.
Offering
The SHA-3 IP core is a high-throughput, area-efficient hardware implementation of the SHA-3/Kaccak cryptographic hashing functions, compliant to NISTS’s FIPS 180-4 and FIPS 202 standards. The core can implement all four fixed-length hash functions (i.e. the SHA3-224, SHA3-256, SHA3-384, and SHA3-512) and both extendable output functions (i.e. SHAKE-128 and SHAKE-256) provisioned by the standards. The function can be dynamically selected at run-time. It’s throughput can optionally be optimized by using input message buffering, which allows it to receive new input while still processing the previous message. Also, the number of hashing rounds per clock is configurable at synthesis time, allowing users to constrain performance to save silicon resources when desired. The SHA-3 IP core can ensure data integrity and/or user authentication in a range of applications including IPsec and TLS/SSL protocol engines, encrypted data storage, secure processing systems, e-commerce, and financial transaction systems.
Offering
The SPMI-CTRL core implements a highly featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus. It supports the latest version (v2.0) of the MIPI-SPMI specification, and is suitable for the implementation of either master or slave nodes in an SPMI bus. The core is designed to minimize the software load on the host processor. Once configured, the core requires no assistance from the host to initialize the bus, connect to bus or disconnect from the bus, grant access of the bus, execute incoming SPMI commands, generate ACK/NACK responses, and check the address and data parity. Although the core only expects the host to provide the outgoing SPMI commands, it provides thorough status information to the host, which can be used for a higher application layer or for debugging purposes. Last received command, outgoing command status, bus status, and node operation status are made available to the host via the core’s registers. Parity errors, unknown commands, or failure of receiving node to provide ACK/NACK response are also reported. Furthermore, the core can be programmed to operate in debug mode, under which the core captures and reports all SPMI bus commands regardless of the destination address. Integration of the core is extremely simple: The core provides access to its registers via a AMBA™ 2 APB slave interface, and converts the incoming SPMI read/write commands to accesses on its AHB master port. This SPMI-AHB bridging allows easy mapping of the SPMI address space to shared memories or peripheral registers. A dedicated interface allows integration with application-specific authentication logic, which can be reduced to just hardwiring the authentication response data. The core uses separate clocks for its APB and AHB bus interfaces, and a separate reference clock source for its internal timer. Clocks are independent to each other, with clean clock domain crossing boundaries, and the only requirement is that the AMBA interface clocks have a frequency larger or equal to the maximum SPMI clock frequency. The core is designed with industry best practices, and its reliability has been proven through rigorous verification.
Offering
The xSPI-MC core is a versatile serial/SPI memory controller, which allows a system to easily detect and access the attached memory device or directly boot from it. The controller core supports most of the proprietary SPI protocols used by Flash and PSRAM devices vendors and is compatible to JEDEC’s eXpanded SPI (xSPI), HyperBus™ and Xccela™ standards. The core allows the system to interface with one or more serial memory devices in one of the following modes: a) in Slave mode by accessing its registers via an AHB slave interface, b) in DMA mode where the system programs the internal DMA engine, and then the core accordingly drives its AHB master interface, c) in Access In-Place (AIP) mode where the core allows the system to directly access the SPI memory address space via an AHB or AXI slave interface, d) in Boot-Image copy mode where after reset the core will autonomously copy an amount of data (boot-image) from the SPI memory to the AHB address space (e.g. on a shadow RAM, or DRAM) using its AHB master interface. The core can work with single, dual, quad, twin-quad, octal, or 16x SPI memory devices. To enable use with memory devices from different vendors, the core offers two ways of configuring the device-specific parameters: a) via registers, where the system is responsible to identify the connected flash device and program the appropriate values to the core's registers and b) by using the auto-configuration feature, where the core will autonomously identify the connected memory device and program itself accordingly. The auto-configuration functionality uses a user-provided memory that stores a list of automatically identifiable devices along with their features. The xSPI-MC can be easily configured to match different application requirements. The instantiation of the DMA engine and the auto-configuration logic, the maximum number of memory devices that the core supports, and the reset values for all configuration registers, are some of the design parameters that can be controlled by means of simple Verilog defines.
Offering
The I3C-T core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Target controller core suitable for any I3C bus topology & compliant with the latest MIPI I3C-BasicSM specification.The highly featured target-only core communicates in Single Data Rate (SDR) mode, but can tolerate High Data Rate (HDR) traffic. It can coexist and communicate with legacy I2C devices, and it can optionally be configured to operate as such in an I3C or I2C bus. The I3C-T needs no firmware support to parse and execute the broadcast or direct Common Command Codes (CCCs) relevant to I3C Basic Targets. It can be assigned a Dynamic Address by the bus controller, or use its legacy I2C static address, it supports Hot Join and is capable of generating In-Band Interrupts when directed by the host to do so.Designed for easy integration, the I3C-T can operate in two different modes. Under normal mode, data from private I3C or legacy I2C write transfers are stored to a FIFO, and made available to the host via an APB subordinate interface. In a similar way, the host provides data to be used for private I3C or legacy I2C read transfers via the core’s APB subordinate interface. Alternatively, the core can operate in I3C-to-AHB bridging mode, where it autonomously converts private I3C or legacy I2C transfers to accesses on its AHB manager port using a simple yet configurable over-I3C protocol. Under the I3C-to-AHB bridging mode, the core needs no software assistance and provides the I3C-controller access to the local AHB bus, enabling remote monitoring, configuration, debug, or data exchange. The selection between normal and bridging operation modes is under software control via the core’s control register.The highly flexible core offers synthesis-time and run-time configuration options, which allow adapting its size and behavior to the application requirements. For example, the AHB-manager interface and the clock domains synchronizers can be removed at synthesis time to reduce the core’s silicon footprint. During run-time, the I3C private data and I2C traffic can be bridged to the core's AHB manager interface or transferred to and from the host via the core's APB subordinate interface. Also, parameters defining the CCCs processing (e.g. own-address, provisional ID, acknowledge for different type CCCs), the over-I3C protocol (i.e. number address bytes, max number of data bytes), and the AHB-manager port behavior (e.g AHB burst type & address wrapping) are all run-time configurable via the core’s registers.The I3C-T core adheres to the industry’s best coding and verification practices to ensure trouble-free implementation in ASIC or FPGA technologies. Technology mapping, constraining, and scan insertion are straight-forward, as the core contains no multi-cycle or false paths, and uses only rising-edge-triggered D-type flip-flops, no tri-states, an asynchronous reset line per clock domain, and clean clock domain crossing modules. Its reliability and low risk have been proven through rigorous verification and FPGA validation.The core is available in synthesizable Verilog format or as a targeted FPGA netlist, and its deliverables include everything required for successful implementation, including a system-Verilog test-bench, synthesis, and simulation scripts, and comprehensive documentation.