SPMI-CTRL: MIPI SPMI Master or Slave Controller
About this offer
The SPMI-CTRL core implements a highly featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus. It supports the latest version (v2.0) of the MIPI-SPMI specification, and is suitable for the implementation of either master or slave nodes in an SPMI bus. The core is designed to minimize the software load on the host processor. Once configured, the core requires no assistance from the host to initialize the bus, connect to bus or disconnect from the bus, grant access of the bus, execute incoming SPMI commands, generate ACK/NACK responses, and check the address and data parity. Although the core only expects the host to provide the outgoing SPMI commands, it provides thorough status information to the host, which can be used for a higher application layer or for debugging purposes. Last received command, outgoing command status, bus status, and node operation status are made available to the host via the core’s registers. Parity errors, unknown commands, or failure of receiving node to provide ACK/NACK response are also reported. Furthermore, the core can be programmed to operate in debug mode, under which the core captures and reports all SPMI bus commands regardless of the destination address. Integration of the core is extremely simple: The core provides access to its registers via a AMBA™ 2 APB slave interface, and converts the incoming SPMI read/write commands to accesses on its AHB master port. This SPMI-AHB bridging allows easy mapping of the SPMI address space to shared memories or peripheral registers. A dedicated interface allows integration with application-specific authentication logic, which can be reduced to just hardwiring the authentication response data. The core uses separate clocks for its APB and AHB bus interfaces, and a separate reference clock source for its internal timer. Clocks are independent to each other, with clean clock domain crossing boundaries, and the only requirement is that the AMBA interface clocks have a frequency larger or equal to the maximum SPMI clock frequency. The core is designed with industry best practices, and its reliability has been proven through rigorous verification.
Technical Specifications
- Category:
- Software and IP Cores: FPGA Intellectual Property Cores: Interface Protocols: Serial
- End Customer Type:
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Small and Medium sized Business
Enterprise
Other
Resources
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Founded in 1993, CAST continues to thrive as the longest-running — and most experienced — independent IP supplier. Our mission has been to provide proven, low-risk IP cores, under simple and flexible licensing terms, coupled with outstanding support. The years of work we have done to perfect IP reuse, improve IP quality standards, and refine sales and business practices yield a product line and a partner network that offer you a better IP experience, today and in the future. Proven, Low-Risk IP: Our goal is to maximize IP benefits for our customers by delivering high-quality, easy-to-use, cost-effective solutions to real system development challenges. CAST quality standards are high, and all our IP undergoes rigorous verification and testing before it gets to you. We use industry-standard verification methodologies, develop and test prototypes, participate in industry collaboration plugfests, and more to ensure proper functioning and smooth integration. Our practices have been extensively tested and proven, as we have helped thousands of customers ship billions of units in hundreds of application areas. Simple, Flexible Licensing: We help you get to work quickly, with fine-tuned project options and licensing terms that ensure smooth legal sign-off. Most CAST IP is available royalty-free, and is extremely cost-effective. Outstanding Support: CAST IP comes with some of the best customer support in the industry. Our goal is to help make you successful, not just sell you IP, and we have the experience and resources to make that happen.
Spmi-ctrl: Mipi Spmi Master Or Slave Controller
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