gpio_config_reg1

Reports settings of various GPIO configuration parameters
Module Instance Base Address Register Address
fpgamgrregs 0xFF706000 0xFF706874

Offset: 0x874

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

encoded_id_width

RO 0x1F
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

gpio_id

RO 0x0

add_encoded_params

RO 0x1

debounce

RO 0x0

porta_intr

RO 0x1

Reserved

hw_porta

RO 0x0

portd_single_ctl

RO 0x1

portc_single_ctl

RO 0x1

portb_single_ctl

RO 0x1

porta_single_ctl

RO 0x1

num_ports

RO 0x0

apb_data_width

RO 0x2

gpio_config_reg1 Fields

Bit Name Description Access Reset
20:16 encoded_id_width

This value is fixed at 32 bits.

Value Description
0x1f Width of ID Field
RO 0x1F
15 gpio_id

Provides an ID code value

Value Description
0x0 GPIO ID Code Register Excluded
RO 0x0
14 add_encoded_params

Fixed to allow the indentification of the Designware IP component.

Value Description
0x1 Enable IP indentification
RO 0x1
13 debounce

The value of this field is fixed to not allow debouncing of the Port A signals.

Value Description
0x0 Debounce is Disabled
RO 0x0
12 porta_intr

The value of this field is fixed to allow interrupts on Port A.

Value Description
0x1 Port A Interrupts Enabled
RO 0x1
8 hw_porta

The value is fixed to enable Port A configuration to be controlled by software only.

Value Description
0x0 Software Configuration Control Enabled
RO 0x0
7 portd_single_ctl

Indicates the mode of operation of Port D to be software controlled only. Ignored because there is no Port D in the GPIO.

Value Description
0x1 Software Enabled Individual Port Control
RO 0x1
6 portc_single_ctl

Indicates the mode of operation of Port C to be software controlled only. Ignored because there is no Port C in the GPIO.

Value Description
0x1 Software Enabled Individual Port Control
RO 0x1
5 portb_single_ctl

Indicates the mode of operation of Port B to be software controlled only. Ignored because there is no Port B in the GPIO.

Value Description
0x1 Software Enabled Individual Port Control
RO 0x1
4 porta_single_ctl

Indicates the mode of operation of Port A to be software controlled only.

Value Description
0x1 Software Enabled Individual Port Control
RO 0x1
3:2 num_ports

The value of this register is fixed at one port (Port A).

Value Description
0x0 Number of GPIO Ports = 1
RO 0x0
1:0 apb_data_width

Fixed to support an APB data bus width of 32-bits.

Value Description
0x2 APB Data Width = 32-bits
RO 0x2