ctrl
Module Instance | Base Address | Register Address |
---|---|---|
fpgamgrregs | 0xFF706000 | 0xFF706004 |
Offset: 0x4
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
cfgwdth RW 0x1 |
axicfgen RW 0x0 |
cdratio RW 0x0 |
prreq RW 0x0 |
confdonepull RW 0x0 |
nstatuspull RW 0x0 |
nconfigpull RW 0x0 |
nce RW 0x0 |
en RW 0x0 |
ctrl Fields
Bit | Name | Description | Access | Reset | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
9 | cfgwdth | This field determines the Configuration Passive Parallel data bus width when HPS configures the FPGA. Only 32-bit Passive Parallel or 16-bit Passive Parallel are supported. When HPS does Normal Configuration, configuration should use 32-bit Passive Parallel Mode. The external pins MSEL must be set appropriately for the configuration selected. For Partial Reconfiguration, 16-bit Passive Parallel must be used.
|
RW | 0x1 | ||||||||||
8 | axicfgen | There are strict SW initialization steps for configuration, partial configuration and error cases. When SW is sending configuration files, this bit must be set before the file is transferred on the AXI bus. This bit enables the DCLK during the AXI configuration data transfers. Note, the AXI and configuration datapaths remain active irregardless of the state of this bit. Simply, if the AXI slave is enabled, the DCLK to the CB will be active. If disabled, the DCLK to the CB will not be active. So AXI transfers destined to the FPGA Manager when AXIEN is 0, will complete normally from the HPS perspective. This field only affects the FPGA if CTRL.EN is 1.
|
RW | 0x0 | ||||||||||
7:6 | cdratio | This field controls the Clock to Data Ratio (CDRATIO) for Normal Configuration and Partial Reconfiguration data transfer from the AXI Slave to the FPGA. For Normal Configuration, the value in this field must be set to be consistent to the implied CD ratio of the MSEL setting. For Partial Reconfiguration, the value in this field must be set to the same clock to data ratio in the options bits in the Normal Configuration file.
|
RW | 0x0 | ||||||||||
5 | prreq | This field is used to assert PR_REQUEST to request partial reconfiguration while the FPGA is in User Mode. This field only affects the FPGA if CTRL.EN is 1.
|
RW | 0x0 | ||||||||||
4 | confdonepull | Pulls down CONF_DONE input to the CB
|
RW | 0x0 | ||||||||||
3 | nstatuspull | Pulls down nSTATUS input to the CB
|
RW | 0x0 | ||||||||||
2 | nconfigpull | The nCONFIG input is used to put the FPGA into its reset phase. If the FPGA was configured, its operation stops and it will have to be configured again to start operation.
|
RW | 0x0 | ||||||||||
1 | nce | This field drives the active-low Chip Enable (nCE) signal to the CB. It should be set to 0 (configuration enabled) before CTRL.EN is set. This field only effects the FPGA if CTRL.EN is 1.
|
RW | 0x0 | ||||||||||
0 | en | Controls whether the FPGA configuration pins or HPS FPGA Manager drive configuration inputs to the CB.
|
RW | 0x0 |