FPGA Manager Module Summary

Registers in the FPGA Manager module accessible via its APB slave

Base Address: 0xFF706000

Register Address Offset	Bit Fields
`stat` `0x0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`msel` `RO 0x8`					`mode` `RW 0x5`
`ctrl` `0x4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`						`cfgwdth` `RW 0x1`	`axicfgen` `RW 0x0`	`cdratio` `RW 0x0`		`prreq` `RW 0x0`	`confdonepull` `RW 0x0`	`nstatuspull` `RW 0x0`	`nconfigpull` `RW 0x0`	`nce` `RW 0x0`	`en` `RW 0x0`
`dclkcnt` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`cnt` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`cnt` `RW 0x0`
`dclkstat` `0xC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`dcntdone` `RW 0x0`
`gpo` `0x10`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RW 0x0`
`gpi` `0x14`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RO 0x0`
`misci` `0x18`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`bootFPGArdy` `RO 0x0`	`bootFPGAfail` `RO 0x0`
`Configuration Monitor (MON) Registers`
`gpio_inten` `0x830`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`				`fpo` `RW 0x0`	`cdp` `RW 0x0`	`nsp` `RW 0x0`	`ncp` `RW 0x0`	`prd` `RW 0x0`	`pre` `RW 0x0`	`prr` `RW 0x0`	`ccd` `RW 0x0`	`crc` `RW 0x0`	`id` `RW 0x0`	`cd` `RW 0x0`	`ns` `RW 0x0`
`gpio_intmask` `0x834`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`				`fpo` `RW 0x0`	`cdp` `RW 0x0`	`nsp` `RW 0x0`	`ncp` `RW 0x0`	`prd` `RW 0x0`	`pre` `RW 0x0`	`prr` `RW 0x0`	`ccd` `RW 0x0`	`crc` `RW 0x0`	`id` `RW 0x0`	`cd` `RW 0x0`	`ns` `RW 0x0`
`gpio_inttype_level` `0x838`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`				`fpo` `RW 0x0`	`cdp` `RW 0x0`	`nsp` `RW 0x0`	`ncp` `RW 0x0`	`prd` `RW 0x0`	`pre` `RW 0x0`	`prr` `RW 0x0`	`ccd` `RW 0x0`	`crc` `RW 0x0`	`id` `RW 0x0`	`cd` `RW 0x0`	`ns` `RW 0x0`
`gpio_int_polarity` `0x83C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`				`fpo` `RW 0x0`	`cdp` `RW 0x0`	`nsp` `RW 0x0`	`ncp` `RW 0x0`	`prd` `RW 0x0`	`pre` `RW 0x0`	`prr` `RW 0x0`	`ccd` `RW 0x0`	`crc` `RW 0x0`	`id` `RW 0x0`	`cd` `RW 0x0`	`ns` `RW 0x0`
`gpio_intstatus` `0x840`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`				`fpo` `RO 0x0`	`cdp` `RO 0x0`	`nsp` `RO 0x0`	`ncp` `RO 0x0`	`prd` `RO 0x0`	`pre` `RO 0x0`	`prr` `RO 0x0`	`ccd` `RO 0x0`	`crc` `RO 0x0`	`id` `RO 0x0`	`cd` `RO 0x0`	`ns` `RO 0x0`
`gpio_raw_intstatus` `0x844`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`				`fpo` `RO 0x0`	`cdp` `RO 0x0`	`nsp` `RO 0x0`	`ncp` `RO 0x0`	`prd` `RO 0x0`	`pre` `RO 0x0`	`prr` `RO 0x0`	`ccd` `RO 0x0`	`crc` `RO 0x0`	`id` `RO 0x0`	`cd` `RO 0x0`	`ns` `RO 0x0`
`gpio_porta_eoi` `0x84C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`				`fpo` `WO 0x0`	`cdp` `WO 0x0`	`nsp` `WO 0x0`	`ncp` `WO 0x0`	`prd` `WO 0x0`	`pre` `WO 0x0`	`prr` `WO 0x0`	`ccd` `WO 0x0`	`crc` `WO 0x0`	`id` `WO 0x0`	`cd` `WO 0x0`	`ns` `WO 0x0`
`gpio_ext_porta` `0x850`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`				`fpo` `RO 0x0`	`cdp` `RO 0x0`	`nsp` `RO 0x0`	`ncp` `RO 0x0`	`prd` `RO 0x0`	`pre` `RO 0x0`	`prr` `RO 0x0`	`ccd` `RO 0x0`	`crc` `RO 0x0`	`id` `RO 0x0`	`cd` `RO 0x0`	`ns` `RO 0x0`
`gpio_ls_sync` `0x860`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`gpio_ls_sync` `RW 0x0`
`gpio_ver_id_code` `0x86C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`gpio_ver_id_code` `RO 0x3230382A`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`gpio_ver_id_code` `RO 0x3230382A`
`gpio_config_reg2` `0x870`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`												`encoded_id_pwidth_d` `RO 0x7`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`encoded_id_pwidth_d` `RO 0x7`	`encoded_id_pwidth_c` `RO 0x7`					`encoded_id_pwidth_b` `RO 0x7`					`encoded_id_pwidth_a` `RO 0xB`
`gpio_config_reg1` `0x874`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`											`encoded_id_width` `RO 0x1F`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`gpio_id` `RO 0x0`	`add_encoded_params` `RO 0x1`	`debounce` `RO 0x0`	`porta_intr` `RO 0x1`	`Reserved`			`hw_porta` `RO 0x0`	`portd_single_ctl` `RO 0x1`	`portc_single_ctl` `RO 0x1`	`portb_single_ctl` `RO 0x1`	`porta_single_ctl` `RO 0x1`	`num_ports` `RO 0x0`		`apb_data_width` `RO 0x2`