gpio_intmask

This register has 12 individual interrupt masks for the MON. Controls whether an interrupt on Port A can create an interrupt for the interrupt controller by not masking it. By default, all interrupts bits are unmasked. Whenever a 1 is written to a bit in this register, it masks the interrupt generation capability for this signal; otherwise interrupts are allowed through. The unmasked status can be read as well as the resultant status after masking.
Module Instance Base Address Register Address
fpgamgrregs 0xFF706000 0xFF706834

Offset: 0x834

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

fpo

RW 0x0

cdp

RW 0x0

nsp

RW 0x0

ncp

RW 0x0

prd

RW 0x0

pre

RW 0x0

prr

RW 0x0

ccd

RW 0x0

crc

RW 0x0

id

RW 0x0

cd

RW 0x0

ns

RW 0x0

gpio_intmask Fields

Bit Name Description Access Reset
11 fpo

Controls whether an interrupt for FPGA_POWER_ON can generate an interrupt to the interrupt controller by not masking it. The unmasked status can be read as well as the resultant status after masking.

Value Description
0x0 Unmask Interrupt
0x1 Mask Interrupt
RW 0x0
10 cdp

Controls whether an interrupt for CONF_DONE Pin can generate an interrupt to the interrupt controller by not masking it. The unmasked status can be read as well as the resultant status after masking.

Value Description
0x0 Unmask Interrupt
0x1 Mask Interrupt
RW 0x0
9 nsp

Controls whether an interrupt for nSTATUS Pin can generate an interrupt to the interrupt controller by not masking it. The unmasked status can be read as well as the resultant status after masking.

Value Description
0x0 Unmask Interrupt
0x1 Mask Interrupt
RW 0x0
8 ncp

Controls whether an interrupt for nCONFIG Pin can generate an interrupt to the interrupt controller by not masking it. The unmasked status can be read as well as the resultant status after masking.

Value Description
0x0 Unmask Interrupt
0x1 Mask Interrupt
RW 0x0
7 prd

Controls whether an interrupt for PR_DONE can generate an interrupt to the interrupt controller by not masking it. The unmasked status can be read as well as the resultant status after masking.

Value Description
0x0 Unmask Interrupt
0x1 Mask Interrupt
RW 0x0
6 pre

Controls whether an interrupt for PR_ERROR can generate an interrupt to the interrupt controller by not masking it. The unmasked status can be read as well as the resultant status after masking.

Value Description
0x0 Unmask Interrupt
0x1 Mask Interrupt
RW 0x0
5 prr

Controls whether an interrupt for PR_READY can generate an interrupt to the interrupt controller by not masking it. The unmasked status can be read as well as the resultant status after masking.

Value Description
0x0 Unmask Interrupt
0x1 Mask Interrupt
RW 0x0
4 ccd

Controls whether an interrupt for CVP_CONF_DONE can generate an interrupt to the interrupt controller by not masking it. The unmasked status can be read as well as the resultant status after masking.

Value Description
0x0 Unmask Interrupt
0x1 Mask Interrupt
RW 0x0
3 crc

Controls whether an interrupt for CRC_ERROR can generate an interrupt to the interrupt controller by not masking it. The unmasked status can be read as well as the resultant status after masking.

Value Description
0x0 Unmask Interrupt
0x1 Mask Interrupt
RW 0x0
2 id

Controls whether an interrupt for INIT_DONE can generate an interrupt to the interrupt controller by not masking it. The unmasked status can be read as well as the resultant status after masking.

Value Description
0x0 Unmask Interrupt
0x1 Mask Interrupt
RW 0x0
1 cd

Controls whether an interrupt for CONF_DONE can generate an interrupt to the interrupt controller by not masking it. The unmasked status can be read as well as the resultant status after masking.

Value Description
0x0 Unmask Interrupt
0x1 Mask Interrupt
RW 0x0
0 ns

Controls whether an interrupt for nSTATUS can generate an interrupt to the interrupt controller by not masking it. The unmasked status can be read as well as the resultant status after masking.

Value Description
0x0 Unmask Interrupt
0x1 Mask Interrupt
RW 0x0