io48_pin_mux_dedicated_io_grp Summary

This set of registers is used to configure the dedicated 1.8 V and 3.0 V HPS I/O pins used for clock, reset, and external flash devices. Only 17 I/O are implemented as dedicated pins.

Base Address: 0xFFD07200

Register Address Offset	Bit Fields
`i_io48_pin_mux_dedicated_io_grp`
`pinmux_dedicated_io_1` `0x0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`
`pinmux_dedicated_io_2` `0x4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`
`pinmux_dedicated_io_3` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`
`pinmux_dedicated_io_4` `0xC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`sel` `RW 0xF`
`pinmux_dedicated_io_5` `0x10`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`sel` `RW 0xF`
`pinmux_dedicated_io_6` `0x14`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`sel` `RW 0xF`
`pinmux_dedicated_io_7` `0x18`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`sel` `RW 0xF`
`pinmux_dedicated_io_8` `0x1C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`sel` `RW 0xF`
`pinmux_dedicated_io_9` `0x20`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`sel` `RW 0xF`
`pinmux_dedicated_io_10` `0x24`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`sel` `RW 0xF`
`pinmux_dedicated_io_11` `0x28`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`sel` `RW 0xF`
`pinmux_dedicated_io_12` `0x2C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`sel` `RW 0xF`
`pinmux_dedicated_io_13` `0x30`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`sel` `RW 0xF`
`pinmux_dedicated_io_14` `0x34`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`sel` `RW 0xF`
`pinmux_dedicated_io_15` `0x38`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`sel` `RW 0xF`
`pinmux_dedicated_io_16` `0x3C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`sel` `RW 0xF`
`pinmux_dedicated_io_17` `0x40`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`sel` `RW 0xF`
`configuration_dedicated_io_bank` `0x100`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to10` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31to10` `RO 0x0`						`VOLTAGE_SEL_CLKRST_IO` `RW 0x0`		`Reserved_7to2` `RO 0x0`						`VOLTAGE_SEL_PERI_IO` `RW 0x0`
`configuration_dedicated_io_1` `0x104`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RO 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RO 0x0`
`configuration_dedicated_io_2` `0x108`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RO 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RO 0x0`
`configuration_dedicated_io_3` `0x10C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RO 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RO 0x8`
`configuration_dedicated_io_4` `0x110`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RW 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RW 0x8`
`configuration_dedicated_io_5` `0x114`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RW 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RW 0x8`
`configuration_dedicated_io_6` `0x118`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RW 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RW 0x8`
`configuration_dedicated_io_7` `0x11C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RW 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RW 0x8`
`configuration_dedicated_io_8` `0x120`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RW 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RW 0x8`
`configuration_dedicated_io_9` `0x124`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RW 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RW 0x8`
`configuration_dedicated_io_10` `0x128`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RW 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RW 0x8`
`configuration_dedicated_io_11` `0x12C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RW 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RW 0x8`
`configuration_dedicated_io_12` `0x130`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RW 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RW 0x8`
`configuration_dedicated_io_13` `0x134`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RW 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RW 0x8`
`configuration_dedicated_io_14` `0x138`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RW 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RW 0x8`
`configuration_dedicated_io_15` `0x13C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RW 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RW 0x8`
`configuration_dedicated_io_16` `0x140`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RW 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RW 0x8`
`configuration_dedicated_io_17` `0x144`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RW 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RW 0x8`