configuration_dedicated_io_10

         This register is used to control the electrical behavior and direction of Dedicated IO 10
Only reset by a cold reset (ignores warm reset).

Module Instance	Base Address	Register Address
`i_io48_pin_mux_dedicated_io_grp`	`0xFFD07200`	`0xFFD07328`

Offset: 0x128

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_31to22` `RO 0x0`										`RTRIM` `RW 0x1`			`INPUT_BUF_EN` `RW 0x2`		`WK_PU_EN` `RW 0x1`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_15to14` `RO 0x0`		`PU_SLW_RT` `RW 0x0`	`PU_DRV_STRG` `RW 0x0`					`Reserved_7to6` `RO 0x0`		`PD_SLW_RT` `RW 0x0`	`PD_DRV_STRG` `RW 0x8`

configuration_dedicated_io_10 Fields

Bit	Name	Description	Access	Reset
31:22	`Reserved_31to22`	Reserved	`RO`	`0x0`
21:19	`RTRIM`	Configuration bits for bias trim 000 : disable 001 : default 010 : trim low 100 : trim high others : invalid/reserved	`RW`	`0x1`
18:17	`INPUT_BUF_EN`	Configuration bits for LVTTL input buffer enable 00 : disable 01 : 1.8V TTL 10 : 2.5V/3.0V TTL 11 : 1.8V TTL	`RW`	`0x2`
16	`WK_PU_EN`	Configuration bit for weak pull up enable 0 : weak pull up disable 1 : weak pull up enable	`RW`	`0x1`
15:14	`Reserved_15to14`	Reserved	`RO`	`0x0`
13	`PU_SLW_RT`	Configuration bit for output pull up slew rate control 0 : slow P slew 1 : fast P slew	`RW`	`0x0`
12:8	`PU_DRV_STRG`	Configuration bits for PMOS pull up drive strength Refer to Table 1 for I/O standards and drive strength settings.	`RW`	`0x0`
7:6	`Reserved_7to6`	Reserved	`RO`	`0x0`
5	`PD_SLW_RT`	Configuration bit for output pull down slew rate control 0 : slow N slew 1 : fast N slew	`RW`	`0x0`
4:0	`PD_DRV_STRG`	Configuration bits for NMOS pull down drive strength. Refer to Table 1 for I/O standards and drive strength settings.	`RW`	`0x8`

Table 1. PU_DRV_STRG and PD_DRV_STRG Bit Settings for HPS Dedicated I/O 10
I/O Standard	Drive Strength (mA)	PU_DRV_STRG[12:8]	PD_DRV_STRG[4:0]
3.0V LVTTL	4	00100	00100
	8	01000	00111
	12	01011	01010
	16	10000	10000
3.0V LVCMOS	4	00111	00111
	8	01111	01111
	12	10111	11001
	16	11111	11111
2.5V LVCMOS	4	00101	00100
	8	01001	01000
	12	01110	01100
	16	10100	10000
1.8V LVCMOS	2	00010	00010
	4	00011	00100
	6	00100	00101
	8	00101	00111
	12	00111	01001
	16	01000	01010