configuration_dedicated_io_bank

         This register is used to control the voltage select for all dedicated IO.

Module Instance	Base Address	Register Address
`i_io48_pin_mux_dedicated_io_grp`	`0xFFD07200`	`0xFFD07300`

Offset: 0x100

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_31to10` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_31to10` `RO 0x0`						`VOLTAGE_SEL_CLKRST_IO` `RW 0x0`		`Reserved_7to2` `RO 0x0`						`VOLTAGE_SEL_PERI_IO` `RW 0x0`

configuration_dedicated_io_bank Fields

Bit	Name	Description	Access	Reset
31:10	`Reserved_31to10`	Reserved	`RO`	`0x0`
9:8	`VOLTAGE_SEL_CLKRST_IO`	Configuration bits for voltage select. This only affects CLK and RST IO. 00 : 3.0V operation 01 : 1.8V operation 10 : 2.5V operation 11 : RSVD	`RW`	`0x0`
7:2	`Reserved_7to2`	Reserved	`RO`	`0x0`
1:0	`VOLTAGE_SEL_PERI_IO`	Configuration bits for voltage select. This only affects peripheral IO (exclude CLK and RST IO). 00 : 3.0V operation 01 : 1.8V operation 10 : 2.5V operation 11 : RSVD	`RW`	`0x0`