io48_pin_mux_shared_3v_io_grp Address Map

This set of registers is used to configure the 48 I/O that are shared between the HPS and the FPGA. These I/O are 3.0 V.
Module Instance Base Address End Address
i_io48_pin_mux_shared_3v_io_grp 0xFFD07000 0xFFD071FF
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Register Offset Width Access Reset Value Description
pinmux_shared_io_q1_1 0x0 32 RW 0xF 
Shared IO 48 Q1 1 Mux Selection Register
pinmux_shared_io_q1_2 0x4 32 RW 0xF 
Shared IO 48 Q1 2 Mux Selection Register
pinmux_shared_io_q1_3 0x8 32 RW 0xF 
Shared IO 48 Q1 3 Mux Selection Register
pinmux_shared_io_q1_4 0xC 32 RW 0xF 
Shared IO 48 Q1 4 Mux Selection Register
pinmux_shared_io_q1_5 0x10 32 RW 0xF 
Shared IO 48 Q1 5 Mux Selection Register
pinmux_shared_io_q1_6 0x14 32 RW 0xF 
Shared IO 48 Q1 6 Mux Selection Register
pinmux_shared_io_q1_7 0x18 32 RW 0xF 
Shared IO 48 Q1 7 Mux Selection Register
pinmux_shared_io_q1_8 0x1C 32 RW 0xF 
Shared IO 48 Q1 8 Mux Selection Register
pinmux_shared_io_q1_9 0x20 32 RW 0xF 
Shared IO 48 Q1 9 Mux Selection Register
pinmux_shared_io_q1_10 0x24 32 RW 0xF 
Shared IO 48 Q1 10 Mux Selection Register
pinmux_shared_io_q1_11 0x28 32 RW 0xF 
Shared IO 48 Q1 11 Mux Selection Register
pinmux_shared_io_q1_12 0x2C 32 RW 0xF 
Shared IO 48 Q1 12 Mux Selection Register
pinmux_shared_io_q2_1 0x30 32 RW 0xF 
Shared IO 48 Q2 1 Mux Selection Register
pinmux_shared_io_q2_2 0x34 32 RW 0xF 
Shared IO 48 Q2 2 Mux Selection Register
pinmux_shared_io_q2_3 0x38 32 RW 0xF 
Shared IO 48 Q2 3 Mux Selection Register
pinmux_shared_io_q2_4 0x3C 32 RW 0xF 
Shared IO 48 Q2 4 Mux Selection Register
pinmux_shared_io_q2_5 0x40 32 RW 0xF 
Shared IO 48 Q2 5 Mux Selection Register
pinmux_shared_io_q2_6 0x44 32 RW 0xF 
Shared IO 48 Q2 6 Mux Selection Register
pinmux_shared_io_q2_7 0x48 32 RW 0xF 
Shared IO 48 Q2 7 Mux Selection Register
pinmux_shared_io_q2_8 0x4C 32 RW 0xF 
Shared IO 48 Q2 8 Mux Selection Register
pinmux_shared_io_q2_9 0x50 32 RW 0xF 
Shared IO 48 Q2 9 Mux Selection Register
pinmux_shared_io_q2_10 0x54 32 RW 0xF 
Shared IO 48 Q2 10 Mux Selection Register
pinmux_shared_io_q2_11 0x58 32 RW 0xF 
Shared IO 48 Q2 11 Mux Selection Register
pinmux_shared_io_q2_12 0x5C 32 RW 0xF 
Shared IO 48 Q2 12 Mux Selection Register
pinmux_shared_io_q3_1 0x60 32 RW 0xF 
Shared IO 48 Q3 1 Mux Selection Register
pinmux_shared_io_q3_2 0x64 32 RW 0xF 
Shared IO 48 Q3 2 Mux Selection Register
pinmux_shared_io_q3_3 0x68 32 RW 0xF 
Shared IO 48 Q3 3 Mux Selection Register
pinmux_shared_io_q3_4 0x6C 32 RW 0xF 
Shared IO 48 Q3 4 Mux Selection Register
pinmux_shared_io_q3_5 0x70 32 RW 0xF 
Shared IO 48 Q3 5 Mux Selection Register
pinmux_shared_io_q3_6 0x74 32 RW 0xF 
Shared IO 48 Q3 6 Mux Selection Register
pinmux_shared_io_q3_7 0x78 32 RW 0xF 
Shared IO 48 Q3 7 Mux Selection Register
pinmux_shared_io_q3_8 0x7C 32 RW 0xF 
Shared IO 48 Q3 8 Mux Selection Register
pinmux_shared_io_q3_9 0x80 32 RW 0xF 
Shared IO 48 Q3 9 Mux Selection Register
pinmux_shared_io_q3_10 0x84 32 RW 0xF 
Shared IO 48 Q3 10 Mux Selection Register
pinmux_shared_io_q3_11 0x88 32 RW 0xF 
Shared IO 48 Q3 11 Mux Selection Register
pinmux_shared_io_q3_12 0x8C 32 RW 0xF 
Shared IO 48 Q3 12 Mux Selection Register
pinmux_shared_io_q4_1 0x90 32 RW 0xF 
Shared IO 48 Q4 1 Mux Selection Register
pinmux_shared_io_q4_2 0x94 32 RW 0xF 
Shared IO 48 Q4 2 Mux Selection Register
pinmux_shared_io_q4_3 0x98 32 RW 0xF 
Shared IO 48 Q4 3 Mux Selection Register
pinmux_shared_io_q4_4 0x9C 32 RW 0xF 
Shared IO 48 Q4 4 Mux Selection Register
pinmux_shared_io_q4_5 0xA0 32 RW 0xF 
Shared IO 48 Q4 5 Mux Selection Register
pinmux_shared_io_q4_6 0xA4 32 RW 0xF 
Shared IO 48 Q4 6 Mux Selection Register
pinmux_shared_io_q4_7 0xA8 32 RW 0xF 
Shared IO 48 Q4 7 Mux Selection Register
pinmux_shared_io_q4_8 0xAC 32 RW 0xF 
Shared IO 48 Q4 8 Mux Selection Register
pinmux_shared_io_q4_9 0xB0 32 RW 0xF 
Shared IO 48 Q4 9 Mux Selection Register
pinmux_shared_io_q4_10 0xB4 32 RW 0xF 
Shared IO 48 Q4 10 Mux Selection Register
pinmux_shared_io_q4_11 0xB8 32 RW 0xF 
Shared IO 48 Q4 11 Mux Selection Register
pinmux_shared_io_q4_12 0xBC 32 RW 0xF 
Shared IO 48 Q4 12 Mux Selection Register