iohmc_ctrl_mmr_top_inst Summary

iohmc_ctrl_mmr_top_inst.register_control

Base Address: 0xF8010000

Register

Address Offset

Bit Fields
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst

reg_dbgcfg0

0x0

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_dbg_mode

RW 0x0

cfg_cmd_driver_sel

RW 0x0

cfg_loopback_en

RW 0x0

cfg_cb_seq_en_fix_en_n

RW 0x0

cfg_prbs_ctrl_sel

RW 0x0

cfg_wdata_driver_sel

RW 0x0

reg_dbgcfg1

0x4

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_dbg_ctrl

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_dbg_ctrl

RW 0x0

reg_dbgcfg2

0x8

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_bist_cmd0_u

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_bist_cmd0_u

RW 0x0

reg_dbgcfg3

0xC

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_bist_cmd0_l

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_bist_cmd0_l

RW 0x0

reg_dbgcfg4

0x10

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_bist_cmd1_u

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_bist_cmd1_u

RW 0x0

reg_dbgcfg5

0x14

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_bist_cmd1_l

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_bist_cmd1_l

RW 0x0

reg_dbgcfg6

0x18

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_dbg_out_sel

RW 0x0

reg_reserve0

0x1C

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_reserve0

RW 0x0

reg_reserve1

0x20

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_reserve1

RW 0x0

reg_reserve2

0x24

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_reserve2

RW 0x0

reg_ctrlcfg0

0x28

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_dbc2_burst_length

RW 0x0

cfg_dbc1_burst_length

RW 0x0

cfg_dbc0_burst_length

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_dbc0_burst_length

RW 0x0

cfg_ctrl_burst_length

RW 0x0

cfg_ac_pos

RW 0x0

cfg_dimm_type

RW 0x0

cfg_mem_type

RW 0x0

reg_ctrlcfg1

0x2C

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_dbc3_enable_dm

RW 0x0

cfg_dbc2_enable_dm

RW 0x0

cfg_dbc1_enable_dm

RW 0x0

cfg_dbc0_enable_dm

RW 0x0

cfg_ctrl_enable_dm

RW 0x0

cfg_dqstrk_en

RW 0x0

cfg_reserve3

RW 0x0

cfg_reorder_read

RW 0x0

cfg_dbc3_reorder_rdata

RW 0x0

cfg_dbc2_reorder_rdata

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_dbc1_reorder_rdata

RW 0x0

cfg_dbc0_reorder_rdata

RW 0x0

cfg_ctrl_reorder_rdata

RW 0x0

cfg_reorder_data

RW 0x0

cfg_dbc3_enable_ecc

RW 0x0

cfg_dbc2_enable_ecc

RW 0x0

cfg_dbc1_enable_ecc

RW 0x0

cfg_dbc0_enable_ecc

RW 0x0

cfg_ctrl_enable_ecc

RW 0x0

cfg_addr_order

RW 0x0

cfg_dbc3_burst_length

RW 0x0

reg_ctrlcfg2

0x30

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_dbc3_pipe_lat

RW 0x0

cfg_dbc2_pipe_lat

RW 0x0

cfg_dbc1_pipe_lat

RW 0x0

cfg_dbc0_pipe_lat

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_dbc0_pipe_lat

RW 0x0

cfg_dbc2ctrl_sel

RW 0x0

cfg_dbc3_ctrl_sel

RW 0x0

cfg_dbc2_ctrl_sel

RW 0x0

cfg_dbc1_ctrl_sel

RW 0x0

cfg_dbc0_ctrl_sel

RW 0x0

cfg_ctrl2dbc_switch1

RW 0x0

cfg_ctrl2dbc_switch0

RW 0x0

cfg_dbc3_output_regd

RW 0x0

cfg_dbc2_output_regd

RW 0x0

cfg_dbc1_output_regd

RW 0x0

cfg_dbc0_output_regd

RW 0x0

cfg_ctrl_output_regd

RW 0x0

reg_ctrlcfg3

0x34

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_cb_memclk_gate_default

RW 0x0

Reserved

cfg_3dsref_ack_on_done

RW 0x0

cfg_geardn_en

RW 0x0

cfg_open_page_en

RW 0x0

cfg_arbiter_type

RW 0x0

cfg_dbc3_dualport_en

RW 0x0

cfg_dbc2_dualport_en

RW 0x0

cfg_dbc1_dualport_en

RW 0x0

cfg_dbc0_dualport_en

RW 0x0

cfg_ctrl_dualport_en

RW 0x0

cfg_dbc3_in_protocol

RW 0x0

cfg_dbc2_in_protocol

RW 0x0

cfg_dbc1_in_protocol

RW 0x0

cfg_dbc0_in_protocol

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_ctrl_in_protocol

RW 0x0

cfg_dbc3_cmd_rate

RW 0x0

cfg_dbc2_cmd_rate

RW 0x0

cfg_dbc1_cmd_rate

RW 0x0

cfg_dbc0_cmd_rate

RW 0x0

cfg_ctrl_cmd_rate

RW 0x0

reg_ctrlcfg4

0x38

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_dbc3_slot_offset

RW 0x0

cfg_dbc2_slot_offset

RW 0x0

cfg_dbc1_slot_offset

RW 0x0

cfg_dbc0_slot_offset

RW 0x0

cfg_ctrl_slot_offset

RW 0x0

cfg_dbc3_slot_rotate_en

RW 0x0

cfg_dbc2_slot_rotate_en

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_dbc1_slot_rotate_en

RW 0x0

cfg_dbc0_slot_rotate_en

RW 0x0

cfg_ctrl_slot_rotate_en

RW 0x0

cfg_pingpong_mode

RW 0x0

cfg_tile_id

RW 0x0

reg_ctrlcfg5

0x3C

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_dbc3_rc_en

RW 0x0

cfg_dbc2_rc_en

RW 0x0

cfg_dbc1_rc_en

RW 0x0

cfg_dbc0_rc_en

RW 0x0

cfg_ctrl_rc_en

RW 0x0

cfg_row_cmd_slot

RW 0x0

cfg_col_cmd_slot

RW 0x0

reg_ctrlcfg6

0x40

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_cs_chip

RW 0x0

reg_ctrlcfg7

0x44

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_wb_backup_entry

RW 0x0

cfg_rb_backup_entry

RW 0x0

Reserved

reg_ctrlcfg8

0x48

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_ck_inv

RW 0x0

cfg_3ds_en

RW 0x0

reg_ctrlcfg9

0x4C

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_dfx_bypass_en

RW 0x0

reg_dramtiming0

0x50

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_mem_clk_disable_entry_cycles

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_mem_clk_disable_entry_cycles

RW 0x0

cfg_power_saving_exit_cycles

RW 0x0

cfg_tcl

RW 0x0

reg_dramodt0

0x54

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_read_odt_chip

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_write_odt_chip

RW 0x0

reg_dramodt1

0x58

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_rd_odt_period

RW 0x0

cfg_wr_odt_period

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_wr_odt_period

RW 0x0

cfg_rd_odt_on

RW 0x0

cfg_wr_odt_on

RW 0x0

reg_sbcfg0

0x5C

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_rld3_refresh_seq1

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_rld3_refresh_seq0

RW 0x0

cfg_self_rfsh_dqstrk_en

RW 0x0

cfg_cb_pdqs_perf_fix_disable

RW 0x0

cfg_cb_3ds_mixed_height_req_fix

RW 0x0

cfg_cb_en_mrnk_rd_fix

RW 0x0

cfg_cb_3ds_mixed_height_ref_ack_disable

RW 0x0

cfg_cb_en_cmd_valid_ungate_fix

RW 0x0

cfg_cb_revert_ref_qual

RW 0x0

cfg_exit_pdn_for_dqstrk

RW 0x0

cfg_no_of_ref_for_self_rfsh

RW 0x0

reg_sbcfg1

0x60

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_reserve9

RW 0x0

cfg_rfsh_post_lower_limit

RW 0x0

cfg_rfsh_post_upper_limit

RW 0x0

cfg_post_rfsh_en

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_rfsh_pre_upper_limit

RW 0x0

cfg_pre_rfsh_en

RW 0x0

cfg_t_param_arf_to_valid

RW 0x0

cfg_dual_ping_pong_en

RW 0x0

reg_sbcfg2

0x64

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_srf_entry_exit_block

RW 0x0

cfg_srf_autoexit_en

RW 0x0

cfg_user_rfsh_en

RW 0x0

cfg_sb_cg_disable

RW 0x0

cfg_mps_dqstrk_disable

RW 0x0

cfg_mps_zqcal_disable

RW 0x0

cfg_srf_zqcal_disable

RW 0x0

reg_sbcfg3

0x68

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_sb_ddr4_mr3

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_sb_ddr4_mr3

RW 0x0

reg_sbcfg4

0x6C

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_sb_ddr4_mr4

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_sb_ddr4_mr4

RW 0x0

reg_sbcfg5

0x70

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_period_dqstrk_ctrl_en

RW 0x0

cfg_short_dqstrk_ctrl_en

RW 0x0

reg_sbcfg6

0x74

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_t_param_dqstrk_to_valid

RW 0x0

cfg_t_param_dqstrk_to_valid_last

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_period_dqstrk_interval

RW 0x0

reg_sbcfg7

0x78

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_rfsh_warn_threshold

RW 0x0

reg_caltiming0

0x7C

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_act_to_act_diff_bg

RW 0x0

cfg_t_param_act_to_act_diff_bank

RW 0x0

cfg_t_param_act_to_act

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_act_to_act

RW 0x0

cfg_t_param_act_to_pch

RW 0x0

cfg_t_param_act_to_rdwr

RW 0x0

reg_caltiming1

0x80

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_rd_to_wr_diff_chip

RW 0x0

cfg_t_param_rd_to_wr

RW 0x0

cfg_t_param_rd_to_rd_diff_bg

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_rd_to_rd_diff_bg

RW 0x0

cfg_t_param_rd_to_rd_diff_chip

RW 0x0

cfg_t_param_rd_to_rd

RW 0x0

reg_caltiming2

0x84

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_wr_to_wr_diff_chip

RW 0x0

cfg_t_param_wr_to_wr

RW 0x0

cfg_t_param_rd_ap_to_valid

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_rd_ap_to_valid

RW 0x0

cfg_t_param_rd_to_pch

RW 0x0

cfg_t_param_rd_to_wr_diff_bg

RW 0x0

reg_caltiming3

0x88

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_wr_to_pch

RW 0x0

cfg_t_param_wr_to_rd_diff_bg

RW 0x0

cfg_t_param_wr_to_rd_diff_chip

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_wr_to_rd_diff_chip

RW 0x0

cfg_t_param_wr_to_rd

RW 0x0

cfg_t_param_wr_to_wr_diff_bg

RW 0x0

reg_caltiming4

0x8C

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_t_param_pdn_to_valid

RW 0x0

cfg_starve_limit

RW 0x0

cfg_t_param_pch_all_to_valid

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_pch_all_to_valid

RW 0x0

cfg_t_param_pch_to_valid

RW 0x0

cfg_t_param_wr_ap_to_valid

RW 0x0

reg_caltiming5

0x90

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_srf_to_zq_cal

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_srf_to_zq_cal

RW 0x0

cfg_t_param_srf_to_valid

RW 0x0

reg_caltiming6

0x94

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_pdn_period

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_pdn_period

RW 0x0

cfg_t_param_arf_period

RW 0x0

reg_caltiming7

0x98

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_mps_to_valid

RW 0x0

cfg_t_param_mrs_to_valid

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_zqcs_to_valid

RW 0x0

cfg_t_param_zqcl_to_valid

RW 0x0

reg_caltiming8

0x9C

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_mmr_cmd_to_valid

RW 0x0

cfg_t_param_rld3_multibank_ref_delay

RW 0x0

cfg_t_param_mps_exit_cke_to_cs

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_mps_exit_cke_to_cs

RW 0x0

cfg_t_param_mps_exit_cs_to_cke

RW 0x0

cfg_t_param_mpr_to_valid

RW 0x0

cfg_t_param_mrr_to_valid

RW 0x0

reg_caltiming9

0xA0

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_t_param_4_act_to_act

RW 0x0

reg_caltiming10

0xA4

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_t_param_16_act_to_act

RW 0x0

reg_dramaddrw

0xA8

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_cs_addr_width

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_bank_group_addr_width

RW 0x0

cfg_bank_addr_width

RW 0x0

cfg_row_addr_width

RW 0x0

cfg_col_addr_width

RW 0x0

reg_sideband0

0xAC

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mr_cmd_trigger

RW 0x0

reg_sideband1

0xB0

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_refresh_req

RW 0x0

reg_sideband2

0xB4

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_zqcal_long_req

RW 0x0

reg_sideband3

0xB8

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_zqcal_short_req

RW 0x0

reg_sideband4

0xBC

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_self_rfsh_req

RW 0x0

reg_sideband5

0xC0

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_dpd_mps_req

RW 0x0

reg_sideband6

0xC4

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mr_cmd_ack

RO 0x0

reg_sideband7

0xC8

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_refresh_ack

RO 0x0

reg_sideband8

0xCC

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_zqcal_ack

RO 0x0

reg_sideband9

0xD0

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_self_rfsh_ack

RO 0x0

reg_sideband10

0xD4

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_dpd_mps_ack

RO 0x0

reg_sideband11

0xD8

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_auto_pd_ack

RO 0x0

reg_sideband12

0xDC

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mr_cmd_rank

RW 0x0

mr_cmd_type

RW 0x0

reg_sideband13

0xE0

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

mr_cmd_opcode

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

mr_cmd_opcode

RW 0x0

reg_sideband14

0xE4

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

mmr_refresh_bank

RW 0x0

reg_sideband15

0xE8

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_stall_rank

RW 0x0

reg_dramsts

0xEC

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

phy_cal_fail

RO 0x0

phy_cal_success

RO 0x0

reg_dbgdone

0xF0

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

dbg_done

RO 0x0

reg_dbgsignals

0xF4

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

dbg_signals_out

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

dbg_signals_out

RO 0x0

reg_dbgreset

0xF8

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

counter_one_reset

RW 0x0

counter_zero_reset

RW 0x0

reg_dbgmatch

0xFC

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

counter_one

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

counter_one

RO 0x0

reg_counter0mask

0x100

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

counter_zero_mask

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

counter_zero_mask

RW 0x0

reg_counter1mask

0x104

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

counter_one_mask

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

counter_one_mask

RW 0x0

reg_counter0match

0x108

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

counter_zero_match

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

counter_zero_match

RW 0x0

reg_counter1match

0x10C

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

counter_one_match

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

counter_one_match

RW 0x0

reg_niosreserve0

0x110

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

nios_reserve0

RW 0x0

reg_niosreserve1

0x114

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

nios_reserve1

RW 0x0

reg_niosreserve2

0x118

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

nios_reserve2

RW 0x0

reg_sbcfg8

0x11C

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_sb_ddr4_mr5

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_sb_ddr4_mr5

RW 0x0

reg_sbcfg9

0x120

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_ddr4_mps_addrmirror

RW 0x0

reg_3ds0

0x124

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_3ds_pr_stag_enable

RW 0x0

cfg_cid_addr_width

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_3ds_lr_num3

RW 0x0

cfg_3ds_lr_num2

RW 0x0

cfg_3ds_lr_num1

RW 0x0

cfg_3ds_lr_num0

RW 0x0

reg_3ds1

0x128

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_3ds_ref2ref_dlr

RW 0x0

reg_3ds2

0x12C

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_chip_id

RW 0x0

reg_pipeline0

0x130

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_cmd_fifo_pipeline_en

RW 0x0

cfg_ac_tile_reg_ena

RW 0x0

cfg_ctl2dbc_tile_reg_ena

RW 0x0

Reserved

cfg_ctl2dbc_reg_ena

RW 0x0

cfg_rb_ptr_reg_ena

RW 0x0

cfg_wb_ptr_reg_ena

RW 0x0

cfg_arbiter_reg_ena

RW 0x0

reg_memclockgating0

0x138

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_memclkgate_setting

RW 0x0

reg_sideband16

0x13C

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

mmr_3ds_refresh_ack

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

mmr_3ds_refresh_ack

RO 0x0