reg_caltiming0

         Calibration Timing 0 Register
      
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF801007C

Size: 32

Offset: 0x7C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_act_to_act_diff_bg

RW 0x0

cfg_t_param_act_to_act_diff_bank

RW 0x0

cfg_t_param_act_to_act

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_act_to_act

RW 0x0

cfg_t_param_act_to_pch

RW 0x0

cfg_t_param_act_to_rdwr

RW 0x0

reg_caltiming0 Fields

Bit Name Description Access Reset
29:24 cfg_t_param_act_to_act_diff_bg
iohmc_ctrl_mmr_top_inst.cfg_t_param_act_to_act_diff_bg[5:0]
Name:Act to Act Diff Bank Group
Description:Active to activate timing on different bank groups, DDR4 only.
RW 0x0
23:18 cfg_t_param_act_to_act_diff_bank
iohmc_ctrl_mmr_top_inst.cfg_t_param_act_to_act_diff_bank[5:0]
Name:Act to Act Diff Bank
Description:Active to activate timing on different banks, for DDR4 same bank group.
RW 0x0
17:12 cfg_t_param_act_to_act
iohmc_ctrl_mmr_top_inst.cfg_t_param_act_to_act[5:0]
Name:Act to Act Same Bank
Description:Active to activate timing on same bank.
RW 0x0
11:6 cfg_t_param_act_to_pch
iohmc_ctrl_mmr_top_inst.cfg_t_param_act_to_pch[5:0]
Name:Act to Precharge Timing
Description:Activate to Precharge Timing.
RW 0x0
5:0 cfg_t_param_act_to_rdwr
iohmc_ctrl_mmr_top_inst.cfg_t_param_act_to_rdwr[5:0]
Name:Act to RW Timing
Description:Activate to Read/write command timing.
RW 0x0