reg_dbgcfg0

Module Instance	Base Address	Register Address
`iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst`	`0xF8010000`	`0xF8010000`

Size: 32

Offset: 0x0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`cfg_dbg_mode` `RW 0x0`				`cfg_cmd_driver_sel` `RW 0x0`	`cfg_loopback_en` `RW 0x0`	`cfg_cb_seq_en_fix_en_n` `RW 0x0`	`cfg_prbs_ctrl_sel` `RW 0x0`	`cfg_wdata_driver_sel` `RW 0x0`

reg_dbgcfg0 Fields

Bit	Name	Description	Access	Reset
8:5	`cfg_dbg_mode`	iohmc_ctrl_mmr_top_inst.cfg_dbg_mode[3:0] Name:Debug Mode Description:4’b0000 – functional mode, TBD	`RW`	`0x0`
4	`cfg_cmd_driver_sel`	iohmc_ctrl_mmr_top_inst.cfg_cmd_driver_sel Name:Cmd Driver Select Description:1’b0 – cmd interface driven by core, 1’b1 - cmd interface driven by MMR	`RW`	`0x0`
3	`cfg_loopback_en`	iohmc_ctrl_mmr_top_inst.cfg_loopback_en Name:Loopback Mode Enable Description:1’b0 – Disable the loopback mode, 1’b1 – Enable the loopback mode for testing	`RW`	`0x0`
2	`cfg_cb_seq_en_fix_en_n`	iohmc_ctrl_mmr_top_inst.cfg_cb_seq_en_fix_en_n Name:Sequencer enable fix Description:Chicken Bit for DBC Fix (DQS Tracking) in Sequencer Enable mode: 1’b0 – Fix Enabled, 1’b1 – Fix Disabled	`RW`	`0x0`
1	`cfg_prbs_ctrl_sel`	iohmc_ctrl_mmr_top_inst.cfg_prbs_ctrl_sel Name:PRBS Control Select Description:1’b0 – PRBS controlled by HMC, 1’b1 – PRBS controlled by sequencer	`RW`	`0x0`
0	`cfg_wdata_driver_sel`	iohmc_ctrl_mmr_top_inst.cfg_wdata_driver_sel Name:Wr Data Driver Select Description:1’b0 – write data from core, 1’b1 – write data from PRBS	`RW`	`0x0`