reg_ctrlcfg4
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF8010038

Size: 32

Offset: 0x38

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_dbc3_slot_offset

RW 0x0

cfg_dbc2_slot_offset

RW 0x0

cfg_dbc1_slot_offset

RW 0x0

cfg_dbc0_slot_offset

RW 0x0

cfg_ctrl_slot_offset

RW 0x0

cfg_dbc3_slot_rotate_en

RW 0x0

cfg_dbc2_slot_rotate_en

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_dbc1_slot_rotate_en

RW 0x0

cfg_dbc0_slot_rotate_en

RW 0x0

cfg_ctrl_slot_rotate_en

RW 0x0

cfg_pingpong_mode

RW 0x0

cfg_tile_id

RW 0x0

reg_ctrlcfg4 Fields

Bit Name Description Access Reset
31:30 cfg_dbc3_slot_offset 
iohmc_ctrl_mmr_top_inst.cfg_dbc3_slot_offset[1:0]
Name:DBC3 Cmd Slot Offset
Description:Enables afi information to be offset by numbers of FR cycles.
Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst, afi_mrnk_write and afi_mrnk_read.
Set this to:
- 2’b00 to have 0 FR cycle offset in HR and QR.
- 2’b01 to have 1 FR cycle offset in QR.
- 2’b10 to have ½ FR cycle offset in HR/QR.
- 2’b11 to have 3 FR cycle offset in QR.
RW 0x0
29:28 cfg_dbc2_slot_offset 
iohmc_ctrl_mmr_top_inst.cfg_dbc2_slot_offset[1:0]
Name:DBC2 Cmd Slot Offset
Description:Enables afi information to be offset by numbers of FR cycles.
Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst, afi_mrnk_write and afi_mrnk_read.
Set this to:
- 2’b00 to have 0 FR cycle offset in HR and QR.
- 2’b01 to have 1 FR cycle offset in QR.
- 2’b10 to have ½ FR cycle offset in HR/QR.
- 2’b11 to have 3 FR cycle offset in QR.
RW 0x0
27:26 cfg_dbc1_slot_offset 
iohmc_ctrl_mmr_top_inst.cfg_dbc1_slot_offset[1:0]
Name:DBC1 Cmd Slot Offset
Description:Enables afi information to be offset by numbers of FR cycles.
Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst, afi_mrnk_write and afi_mrnk_read.
Set this to:
- 2’b00 to have 0 FR cycle offset in HR and QR.
- 2’b01 to have 1 FR cycle offset in QR.
- 2’b10 to have ½ FR cycle offset in HR/QR.
- 2’b11 to have 3 FR cycle offset in QR.
RW 0x0
25:24 cfg_dbc0_slot_offset 
iohmc_ctrl_mmr_top_inst.cfg_dbc0_slot_offset[1:0]
Name:DBC0 Cmd Slot Offset
Description:Enables afi information to be offset by numbers of FR cycles.
Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst, afi_mrnk_write and afi_mrnk_read.
Set this to:
- 2’b00 to have 0 FR cycle offset in HR and QR.
- 2’b01 to have 1 FR cycle offset in QR.
- 2’b10 to have ½ FR cycle offset in HR/QR.
- 2’b11 to have 3 FR cycle offset in QR.
RW 0x0
23:22 cfg_ctrl_slot_offset 
iohmc_ctrl_mmr_top_inst.cfg_ctrl_slot_offset[1:0]
Name:Cmd Slot Offset
Description:Enables afi information to be offset by numbers of FR cycles.
Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst, afi_mrnk_write and afi_mrnk_read.
Set this to:
- 2’b00 to have 0 FR cycle offset in HR and QR.
- 2’b01 to have 1 FR cycle offset in QR.
- 2’b10 to have ½ FR cycle offset in HR/QR.
- 2’b11 to have 3 FR cycle offset in QR.
RW 0x0
21:19 cfg_dbc3_slot_rotate_en 
iohmc_ctrl_mmr_top_inst.cfg_dbc3_slot_rotate_en[2:0]
Name:DBC3 Slot Rotate Enable
Description:DBC3 slot rotate enable: Bit[0] controls write, 1’b0 – disable (fixed slot), 1’b1 – enable (allow cmd slot rotation). Bit[1] controls read, 1’b0 – disable (fixed slot), 1’b1 – enable (allow cmd slot rotation). Bit[2] controls always rotate, 1’b0 disabled (fixed slot), 1’b1 – enable (always rotate cmd)
RW 0x0
18:16 cfg_dbc2_slot_rotate_en 
iohmc_ctrl_mmr_top_inst.cfg_dbc2_slot_rotate_en[2:0]
Name:DBC2 Slot Rotate Enable
Description:DBC2 slot rotate enable: Bit[0] controls write, 1’b0 – disable (fixed slot), 1’b1 – enable (allow cmd slot rotation). Bit[1] controls read, 1’b0 – disable (fixed slot), 1’b1 – enable (allow cmd slot rotation). Bit[2] controls always rotate, 1’b0 disabled (fixed slot), 1’b1 – enable (always rotate cmd)
RW 0x0
15:13 cfg_dbc1_slot_rotate_en 
iohmc_ctrl_mmr_top_inst.cfg_dbc1_slot_rotate_en[2:0]
Name:DBC1 Slot Rotate Enable
Description:DBC1 slot rotate enable: Bit[0] controls write, 1’b0 – disable (fixed slot), 1’b1 – enable (allow cmd slot rotation). Bit[1] controls read, 1’b0 – disable (fixed slot), 1’b1 – enable (allow cmd slot rotation). Bit[2] controls always rotate, 1’b0 disabled (fixed slot), 1’b1 – enable (always rotate cmd)
RW 0x0
12:10 cfg_dbc0_slot_rotate_en 
iohmc_ctrl_mmr_top_inst.cfg_dbc0_slot_rotate_en[2:0]
Name:DBC0 Slot Rotate Enable
Description:DBC0 slot rotate enable: Bit[0] controls write, 1’b0 – disable (fixed slot), 1’b1 – enable (allow cmd slot rotation). Bit[1] controls read, 1’b0 – disable (fixed slot), 1’b1 – enable (allow cmd slot rotation). Bit[2] controls always rotate, 1’b0 disabled (fixed slot), 1’b1 – enable (always rotate cmd)
RW 0x0
9:7 cfg_ctrl_slot_rotate_en 
iohmc_ctrl_mmr_top_inst.cfg_ctrl_slot_rotate_en[2:0]
Name:Cmd Slot Rotate Enable
Description:Cmd slot rotate enable: Bit[0] controls write, 1’b0 – disable (fixed slot), 1’b1 – enable (allow cmd slot rotation). Bit[1] controls read, 1’b0 – disable (fixed slot), 1’b1 – enable (allow cmd slot rotation). Bit[2] controls always rotate. 1’b0 disabled (fixed slot), 1’b1 – enable (always rotate cmd)
RW 0x0
6:5 cfg_pingpong_mode 
iohmc_ctrl_mmr_top_inst.cfg_pingpong_mode[1:0]
Name:Ping Pong mode
Description:Ping Pong mode: 2’b00 – Ping Pong support off, 2’b01 – Ping Pong master0 (driving C/A pins), 2’b10 – Ping Pong master1.
RW 0x0
4:0 cfg_tile_id 
iohmc_ctrl_mmr_top_inst.cfg_tile_id[4:0]
Name:Tile ID
Description:Tile ID
RW 0x0