reg_ctrlcfg3
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF8010034

Size: 32

Offset: 0x34

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_cb_memclk_gate_default

RW 0x0

Reserved

cfg_3dsref_ack_on_done

RW 0x0

cfg_geardn_en

RW 0x0

cfg_open_page_en

RW 0x0

cfg_arbiter_type

RW 0x0

cfg_dbc3_dualport_en

RW 0x0

cfg_dbc2_dualport_en

RW 0x0

cfg_dbc1_dualport_en

RW 0x0

cfg_dbc0_dualport_en

RW 0x0

cfg_ctrl_dualport_en

RW 0x0

cfg_dbc3_in_protocol

RW 0x0

cfg_dbc2_in_protocol

RW 0x0

cfg_dbc1_in_protocol

RW 0x0

cfg_dbc0_in_protocol

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_ctrl_in_protocol

RW 0x0

cfg_dbc3_cmd_rate

RW 0x0

cfg_dbc2_cmd_rate

RW 0x0

cfg_dbc1_cmd_rate

RW 0x0

cfg_dbc0_cmd_rate

RW 0x0

cfg_ctrl_cmd_rate

RW 0x0

reg_ctrlcfg3 Fields

Bit Name Description Access Reset
30 cfg_cb_memclk_gate_default 
iohmc_ctrl_mmr_top_inst.cfg_cb_memclk_gate_default
Name:Memory Clock Gating Default Value Chicken Bit
Description:When set to 0, both mem_ck/mem_ck_n are driven to LOW when clock gating is enabled.
When set to 1, mem_ck is driven to LOW and mem_ck_n is driven to HIGH when clock gating is enabled.
RW 0x0
28 cfg_3dsref_ack_on_done 
iohmc_ctrl_mmr_top_inst.cfg_3dsref_ack_on_done
Name:3DS Refresh Ack on Done
Description:When set to 1, the ack pulse for 3DS Refresh is asserted when tRFC has expired.
When set to 0, the ack pulse for 3DS Refresh is asserted on the launch of Refresh command to DRAM.
RW 0x0
27 cfg_geardn_en 
iohmc_ctrl_mmr_top_inst.cfg_geardn_en
Name:Gear Down Mode Enable
Description:Set to 1 to enable the gear down mode for DDR4
RW 0x0
26 cfg_open_page_en 
iohmc_ctrl_mmr_top_inst.cfg_open_page_en
Name:Open Page Policy Enable
Description:Set to 1 to enable the open page policy when command reordering is disabled (cfg_cmd_reorder=0). This bit does not matter when cfg_cmd_reorder is 1.
RW 0x0
25 cfg_arbiter_type 
iohmc_ctrl_mmr_top_inst.cfg_arbiter_type
Name:Arbiter Type
Description:Indicates controller arbiter operating mode. Set this to:
- 1’b0 for non-quasi (single cmd) mode
- 1’b1 for quasi (dual cmd) mode
RW 0x0
24 cfg_dbc3_dualport_en 
iohmc_ctrl_mmr_top_inst.cfg_dbc3_dualport_en
Name:Reserved
Description:TBD
RW 0x0
23 cfg_dbc2_dualport_en 
iohmc_ctrl_mmr_top_inst.cfg_dbc2_dualport_en
Name:Reserved
Description:TBD
RW 0x0
22 cfg_dbc1_dualport_en 
iohmc_ctrl_mmr_top_inst.cfg_dbc1_dualport_en
Name:Reserved
Description:TBD
RW 0x0
21 cfg_dbc0_dualport_en 
iohmc_ctrl_mmr_top_inst.cfg_dbc0_dualport_en
Name:Reserved
Description:TBD
RW 0x0
20 cfg_ctrl_dualport_en 
iohmc_ctrl_mmr_top_inst.cfg_ctrl_dualport_en
Name:Reserved
Description:TBD
RW 0x0
19 cfg_dbc3_in_protocol 
iohmc_ctrl_mmr_top_inst.cfg_dbc3_in_protocol
Name:DBC3 Input interface protocol
Description:1’b0 – AST , 1’b1 – AMM
RW 0x0
18 cfg_dbc2_in_protocol 
iohmc_ctrl_mmr_top_inst.cfg_dbc2_in_protocol
Name:DBC2 Input interface protocol
Description:1’b0 – AST , 1’b1 – AMM
RW 0x0
17 cfg_dbc1_in_protocol 
iohmc_ctrl_mmr_top_inst.cfg_dbc1_in_protocol
Name:DBC1 Input interface protocol
Description:1’b0 – AST , 1’b1 – AMM
RW 0x0
16 cfg_dbc0_in_protocol 
iohmc_ctrl_mmr_top_inst.cfg_dbc0_in_protocol
Name:DBC0 Input interface protocol
Description:1’b0 – AST , 1’b1 – AMM
RW 0x0
15 cfg_ctrl_in_protocol 
iohmc_ctrl_mmr_top_inst.cfg_ctrl_in_protocol
Name:Control path Input interface protocol
Description:1’b0 – AST , 1’b1 – AMM
RW 0x0
14:12 cfg_dbc3_cmd_rate 
iohmc_ctrl_mmr_top_inst.cfg_dbc3_cmd_rate[2:0]
Name:DBC3 – Command Rate
Description:3’b010 – HALF rate. 3’b100 – Quarter rate. The remaining values are reserved.
RW 0x0
11:9 cfg_dbc2_cmd_rate 
iohmc_ctrl_mmr_top_inst.cfg_dbc2_cmd_rate[2:0]
Name:DBC2 – Command Rate
Description:3’b010 – HALF rate. 3’b100 – Quarter rate. The remaining values are reserved.
RW 0x0
8:6 cfg_dbc1_cmd_rate 
iohmc_ctrl_mmr_top_inst.cfg_dbc1_cmd_rate[2:0]
Name:DBC1 – Command Rate
Description:3’b010 – HALF rate. 3’b100 – Quarter rate. The remaining values are reserved.
RW 0x0
5:3 cfg_dbc0_cmd_rate 
iohmc_ctrl_mmr_top_inst.cfg_dbc0_cmd_rate[2:0]
Name:DBC0 – Command Rate
Description:3’b010 – HALF rate. 3’b100 – Quarter rate. The remaining values are reserved.
RW 0x0
2:0 cfg_ctrl_cmd_rate 
iohmc_ctrl_mmr_top_inst.cfg_ctrl_cmd_rate[2:0]
Name:Control path – Command Rate
Description:3’b010 – HALF rate. 3’b100 – Quarter rate. The remaining values are reserved.
RW 0x0