Cyclone® V FPGA and SoC FPGA

Tailored for High-Volume, Cost-Sensitive Applications

With Cyclone® V FPGA, you can get the power, cost and performance levels you need for high-volume applications including protocol bridging, motor control drives, broadcast video converter and capture cards and handheld devices. Learn more about the advantages of Cyclone® V FPGA in a variety of market segments.

SoC FPGA–Your Customizable ARM* Processor-Based SoC

SoC FPGA lets you reduce system power, system cost and board space by integrating a HPS – consisting of processors, peripherals and memory controller – with the FPGA fabric using a high-bandwidth interconnect backbone. The combination of the HPS with Intel's 28 nm low-power FPGA fabric provide the performance and ecosystem of an applications-class ARM* processor with the flexibility, low cost and low power consumption of the Cyclone® V FPGA.

Reducing Total System Cost Through Integration

Because Cyclone® V FPGA integrates an abundance of hard intellectual property (IP) blocks, you can differentiate and do more with less overall system cost, power and design time. Key hard IP blocks include the following:

• Hard memory controllers supporting 400 MHz DDR3 SDRAM with optional error correction code (ECC) support.
• PCI Express* (PCIe*) Gen2 with multifunction support.
• Variable-precision digital signal processing (DSP) blocks.
• HPS Dual-core ARM* Cortex*-A9 MPCore* processor.

Industry-Leading Low Power and Low System Cost

• Up to 40 percent lower total power compared with Cyclone® IV GX FPGA.
• Lowest power serial transceivers with 88 mW maximum power consumption per channel at 5 Gbps.
  
• Over 4,000 MIPS (Dhrystones 2.1 benchmark) processing performance for under 1.8 W (for SoC FPGA).
• Lower power due to increased use of hard IP blocks.

Also lowering cost – the FPGA requires only two power regulator voltages and come in wire-bond packages with small form factor options.

ARM*-Based HPS

The Cyclone® V SoC FPGA HPS consists of a dual-core ARM* Cortex*-A9 MPCore* processor, a rich set of peripherals and a multiport memory controller shared with logic in the FPGA, giving you the flexibility of programmable logic and the cost savings of hard intellectual property (IP) due to:

• Single- or dual-core processor with up to 925 MHz maximum frequency.
• Hardened embedded peripherals eliminate the need to implement these functions in programmable logic, leaving more FPGA resources for application-specific custom logic and reducing power consumption.
• Hardened multiport memory controller, shared by the processor and FPGA logic, supports DDR2, DDR3 and LPDDR2 devices with integrated error correction code (ECC) support for high-reliability and safety-critical applications.

High-Bandwidth Interconnect

High-throughput datapaths between the HPS and FPGA fabric provide interconnect performance not possible in two-chip solutions. This tight integration provides:

• Over 100 Gbps peak bandwidth.
• Integrated data coherency.
• Significant system power savings by eliminating the external I/O paths between the processor and the FPGA.

Flexible FPGA Fabric

The FPGA logic fabric lets you differentiate your system by implementing custom IP or off-the-shelf preconfigured IP from Intel or its partners into your designs. This allows you to:

• Adapt quickly to varying or changing interface and protocol standards.
• Add custom hardware in the FPGA to accelerate time-critical algorithms and create a compelling competitive edge.
• Quickly deploy a custom ARM* processor without the extensive design, verification and non-recurring engineering (NRE) costs required in ASICs.

Architecture Matters

Because Cyclone® V SoC FPGA integrates many hard IP blocks, you can lower your overall system cost, power and design time. SoC FPGA is more than the sum or its' parts. How the processor and FPGA systems work together matters greatly to your system’s performance, reliability and flexibility. It is designed to:

• Preserve the flexibility of processor boot or FPGA configuration sequence, system response to processor reset and independent memory interfaces of a two-chip solution.
• Maintain data integrity and reliability with integrated ECC.
• Protect DRAM memory shared by the processor and FPGA with an integrated memory protection unit.
• Enable system-level debug with adaptive debugging for unmatched visibility and control of the whole device.