Cyclone® V SE SoC FPGA
Cyclone® V SE FPGA is optimized for low system cost and power with integrated ARM® Cortex®-A9 MPCore Processor System for 614 Mbps to 3.125 Gbps transceiver applications.
Cyclone® V SE SoC FPGA
Benefits
Do More with Less Power, Design Time, and Cost
Built on TSMC's 28 nm low-power (28LP) process technology, including an abundance of hard intellectual property (IP) blocks, allowing you to differentiate and do more.
Logic Integration and Differentiation Capabilities
It offers an 8-input adaptive logic module (ALM) and variable-precision digital signal processing (DSP) blocks, allowing up to 13.59 megabits (Mb) of embedded memory.
Hard processor system (HPS) with integrated ARM® Cortex®-A9 MPCore processor
Tight integration of a dual-core ARM® Cortex®-A9 MPCore processor, hard IP, and an FPGA in a single Cyclone® V system-on-a-chip (SoC). It supports over 128 Gbps peak bandwidth with integrated data coherency between the processor and the FPGA fabric.
Applications
Energy Efficiency for Next Generation Drives
Addresses complexity and performance requirements: fast control loops; DSP and computational performance, support multiple Industrial Ethernet (IE) protocols, scalability for multi-axes control, and integrated drive systems. Improves time to market through scalability, flexibility and by hardware and design reuse, and support functional safety IP and tool flow: saves up to 24 months in Safety Certification process.
IP Closed Circuit Television Surveillance
Capable of handling the sensor interface (glueless for parallel connectivity or high speed serial), the entire image sensor pipeline or ISP, the unique image processing for Wide Dynamic Range CMOS sensors, optimized motor control for pan & tilt, on-chip video compression, scaling, analytics, Ethernet controllers and the ability to connect to off-chip encoders or PHY devices for the broadcast, analog or IP camera markets.
High Definition (HD) IP Camera
Future generation HD IP cameras to bring integration of the DSP (image processing) and FPGA (HD video analytics) into a single SoC FPGA chip providing HD 1080p video analytics with wide dynamic range. The HD video analytics could run on one of the ARM cores with additional logic in the FPGA fabric. In this case, Wide Dynamic Range is added to the image signal processing in the SoC FPGA.
Key Features
Embedded Memory Blocks
- M10K: 10-kilobits (Kb) memory blocks with soft error correction code (ECC).
- Memory logic array block (MLAB): 640-bit distributed LUTRAM where you can use up to 25% of the ALMs as MLAB memory.
General-purpose I/Os
- 875 megabits per second (Mbps) low-voltage differential signaling (LVDS) receiver and 840 Mbps LVDS transmitter.
- 400 MHz/800 Mbps external memory interface.
- On-chip termination (OCT).
- 3.3 V support with up to 16 mA drive strength.
External Memory Interface
In the Cyclone® V SoC devices, an additional hard memory controller in the HPS supports DDR3, DDR2, and LPDDR2 SDRAM devices.
Hard Processor System (HPS)
The HPS consists of a dual-core Arm* Cortex* -A9 MPCore* processor, a rich set of peripherals, and a shared multiport SDRAM memory controller.
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