Creonic is an ISO 9001:2015 certified provider of ready-for-use IP cores for wired, wireless, fiber, and free-space optical communications. All relevant digital signal processing algorithms are covered, including, but not limited to, forward error correction, modulation, equalization, and demodulation. We offer the richest product portfolio in this field, covering standards like 3GPP 5G, DVB-S2X, DVB-RCS2, CCSDS, and Wifi. The products are applicable for ASIC and FPGA technologies and comply with the highest requirements with respect to quality and performance. As the richest in this field, the IP core product portfolio is used by dozens of customers worldwide in satellite modems and satellites. With Creonic’s chip designs, companies from start-ups to global corporations can realize their NewSpace goals. For more information please visit our website at www.creonic.com
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The Creonic 5G LDPC Encoder IP Core provides a perfect solution for this new LDPC structure with a high level of flexibility while maintaining high throughput and low latency as required by the standard.
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The Creonic Fast Fourier Transform IP Core implements the Decimation in Frequency - Fast Fourier Transform based on the Cooley-Tukey algorithm. The FFT core expects complex samples as input and provides transformed complex samples as output. It performs the transform using log₂(transform length) stages in pipeline.
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The ITU-T G.9804.2 Recommendation defines the common transmission convergence (ComTC) layer for higher speed passive optical networks. As part of the Forward Error Correction (FEC) in the ComTC layer. The Creonic ITU 25G PON LDPC Encoder and Decoder support the default LDPC (17280, 14592) coding scheme, as well as the optional LDPC (17152, 14592) scheme. The IP cores are available for ASIC and FPGAs.
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The Creonic DVB-S2X modulator is a low-complexity high-performance solution that allows for symbol rates of up to 250 MSymb/s (2 Gbit/s for 256-APSK) on state-of-the-art FPGAs. The IP core performs all tasks of the inner transmitter and complements the Creonic DVB-S2X receiver solutions (DVB-S2X demodulator and DVB-S2X LDPC/BCH decoder). Additionally, the core comes with a license option for the Creonic DVB-CID modulator.DVB-S2X is the next generation satellite transmission standard which is an extended version of its well-established predecessor DVB-S2. The new specification allows for spectral efficiency gains of up to 50% by offering lower roll-off factors, higher modulations and a finer code rate granularity compared to DVB-S2.
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The Creonic DVB-S2X demodulator is a low-complexity high-performance solution that allows for symbol rates of up to 100 MSymb/s on state-of-the-art FPGAs. DVB-S2X is the next generation satellite transmission standard which is an extended version of its well-established predecessor DVB-S2. The new specification allows for spectral efficiency gains of up to 50% by offering lower roll-off factors, higher modulations and a finer code rate granularity compared to DVB-S2.
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The CCSDS AR4JA LDPC codec supports code rates 1/2, 2/3, and 4/5 each with uncoded block sizes of 1024, 4096, and 16384 bits. It was designed particularly for deep space missions, but the excellent error correction performance makes it the ideal fit for additional applications with highest demands on forward error correction. Applications Near-Earth and Deep-Space communication, space link communication, microwave links, optical links, Further applications with the highest demands on forward error correction. Standard features the core supports uncoded block sizes of 1024, 4096, and 16384 bits. Code rates of 1/2, 2/3, and 4/5. Compliant with “TM synchronization and channel coding, recommended standard CCSDS 131.0-B-3, Blue Book” your benefits. Gains more than 3 dB compared to Viterbi decoders. Low-power and low-complexity design. Layered LDPC decoder architecture, for faster convergence behavior. Block-to-block on-the-fly configuration. Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy. Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance. Collection of statistic information (number of iterations, decoding success, number of modified bits). Available for ASIC and FPGAs. Deliverable includes VHDL source code or synthesized netlist, VHDL test bench, and bit-accurate Matlab, C or C++ simulation model.
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The Creonic DVB-S2X high performance wideband modulator performs all tasks of an inner transmitter. The modulator expects BB frames after mode adaptation as input and performs stream adaptation, FEC encoding, mapping, PL framing and modulation. In addition the core can perform baseband interpolation and output gain adjustment. The output of the core is designed to be followed by a DAC and RF front end.
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5G NR is the mobile broadband standard of the 5th generation. A new rate compatible structure for LDPC codes are employed for channel coding to fulfill the broad applications supported by the standard. Creonic's 5G LDPC Decoder IP Core provides a perfect solution for this new LDPC structure with high level of flexibility while maintaining high throughput and low latency as required by the standard.
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DVB-S2 (Digital video broadcast - satellite 2nd generation) is an ETSI standard of the second generation for digital data transmission via satellites. It was published in 2005. Being the first standard of the second generation DVB standards (DVB-S2/-T2/-C2). Because of its capacity-approaching forward error correction, today DVB-S2 is the de-facto standard in satellite communication and other applications. The Creonic DVB-S2 IP core integrates the forward error correction as defined by the standard (including LDPC and BCH decoder).
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DVB-RCS (Digital video broadcast - interaction channel for satellite distribution systems) is an established ETSI standard for digital data transmission via satellites. It uses a 8-state double-binary turbo decoder that has an excellent error correction performance. This outstanding performance of the DVB-RCS turbo decoder makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.
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The Creonic DVB-S2X high performance multi-carrier demodulator performs all tasks of an inner receiver while processing up to 36 carriers in parallel. The demodulator expects quantized real samples in an intermediate frequency (IF) from an analog-digital-converter (ADC). It separates the carriers with FFT/IFFT processing, and then performs all further demodulation steps in a time-multiplexed way. It recovers timing, frequency and phase of the complex mapped symbols for each carrier individually. In addition, the core handles PL frame recovery and PL deframing. The demodulator can work with the Creonic DVB-S2X LDPC/BCH decoder IP core by inserting a glue logic between the cores. The glue logic can be provided upon customer’s request.
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The Creonic DVB-S2X high performance wideband demodulator performs all tasks of an inner receiver and achieves throughputs of up to 500 Msymb/s on state of the art FPGAs. The demodulator expects the quantized, complex baseband samples from an analog-digital-converter (ADC) and recovers timing, frequency and phase of the complex mapped symbols. In addition the core handles PL frame recovery and PL de-framing. The output of the demodulator perfectly fits the Creonic DVB-S2X forward error correction IP core that implements LDPC and BCH decoding
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GEO-Mobile Radio (GMR) is an ETSI standard for satellite phones. The Creonic GMR Decoder IP core supports the PNB2 burst packets that were added in GMR Release 2 (GMPRS-1) and use LDPC codes for the first time. The same burst modes and LDPC codes are also in GMR Re- lease 3 (GMR-3G). The Creonic GMR LDPC decoder IP core is a field-proven solution.
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The Creonic DVB-S2X Wideband decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 500 MSymb/s on state-of-the-art FPGAs.
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The IEEE 802.15 working group specifies standards targeting the wireless personal area network (WPAN). Task group 3 of the working group focuses on high data rates within WPAN. The task group 3c defined a new millimeter-wave-based alternative physical layer (PHY) for the IEEE 802.15.3-2003 standard. This standard (IEEE 802.15.3c-2009) operates at 60 GHz and offers data rates of multiple Gbit/s for applications such as high speed internet access or streaming content download. The task group adopted LDPC codes for these high data rate modes within the single carrier (SC) mode and the high speed interface (HSI) mode. The Creonic IEEE 802.15.3c LDPC Decoder IP supports all LDPC codes with a codeword size of 672 bits as defined by the standard.
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The recommended CCSDS 131.2-B-1 standard introduces a Serial Concatenated Convolutional Code (SCCC). Main goal of this code is to allow an efficient use of available bandwidth, by allowing to select from 27 valid configurations with a wide range of constellations, block lengths and code rates. The outstanding error correction performance of the SCCC code in combination with the high data rates makes this IP core the ideal fit for further applications where high throughput and high spectral efficiency is key for operation.
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The Creonic Wideband Digital Down Converter (DDC) digitally converts the input signal at IF frequency down to baseband by multiplying input samples with sine/cosine waves generated by numerical controlled oscillators (NCO). Down converted samples are then decimated by a factor ranging from 2 to 2048 with multiplying step of 2. A CIC and 4 stages of half band filters are integrated within the decimator. The core accepts a real signal at input and provides complex I/Q baseband data at the output. The parallel architecture of the core allows for an input throughput up to 2.4 Gsps, data symbol rate up to 540 Msymb/s, making it a perfect fit for ultra high throughput applications such as wideband DVB-S2X communication.
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The WiGig standard (IEEE 802.11ad) delivers data rates of up to 7 Gbit/s and hence outperforms the current IEEE 802.11n standard by more than 10x. It uses the 60 GHz band to enable short range communication and interoperability between a broad set of applications and platforms. The Creonic WiGig LDPC decoder is designed in particular to deliver highest throughputs in the multi-gigabit domain with a small footprint. At the same time it provides outstanding error correction performance, resulting in a low energy consumption and increasing range of wireless transmission. Its unique pipeline architecture can be customized at design-time to deliver best performance on any target technology. Insertion, removal and balancing of pipeline stages within the IP core is flexible and allows for optimization of required routing resources, path delays between pipeline stages, throughput, and footprint at the same time.
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The Creonic AWGN Channel IP is a noise generator capable of processing up to a maximum of 256 symbols in parallel. The IP was developed with the aim of allowing the performance evaluation of a digital communication system in the presence of additive white gaussian noise. The emphasis is on evaluating systems with low bit error rates. Unlike a software-based AWGN generator, which might take several hours and even days for the stated purpose, a hardware based AWGN generator requires significantly less time. Runtime is reduced by several orders of magnitude. Applications digital communication systems for which an AWGN channel is required. Your benefits design time configuration of the number of symbols in parallel, quantization of input and output and pre-calculation of standard variation, for adjustment of resource utilization. Low-power and low-complexity design. AXI4-Stream interface for easy integration. Available for ASIC and FPGAs. Deliverable includes VHDL source code or synthesized netlist, VHDL test bench, and bit-accurate Matlab, C or C++ simulation model, HDL simulation models e.g. for Aldec’s Riviera-PRO.
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DVB-RCS2 (digital video broadcast - second generation DVB interactive satellite system) is the latest ETSI standard of the second generation for digital data transmission via satellites. It uses a new 16-state double- binary turbo decoder that significantly outperforms its dated 8-state counterpart of DVB-RCS. DVB-RCS2 is the first standard to adopt these highest performance turbo codes. New modulation schemes (8-PSK and 16-QAM) help to increase spectral efficiency even further. The outstanding error correction performance of the DVB-RCS2 turbo decoder makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.
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Polar codes are a trending family of forward error correction codes currently gaining a place in the realm of digital communications, which exhibit a particularly high performance while requiring a low-complexity implementation. They were first adopted by the 3GPP 5G NR standard. The Creonic Polar Encoder IP core is a scalable solution featuring code-rate flexibility, high throughput and very low latency on state-of-the-art FPGAs. Since a polar encoder normally requires information data to be presented in a certain way at its input, the Creonic Polar Encoder IP takes care of this in a pre-encoding stage. This important feature, with aid of AXI4-Stream interface ports, allows a very straight-forward integration of the core into any system.
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The solution from Creonic for data rates of up to 1 Gbit/s offers outstanding efficiency in terms of implementation complexity. Area and energy efficiency played a decisive role during the LDPC code design process. With this unified approach not only outstanding efficiency is obtained, but also excellent error correction performance, outperforming viterbi decoders by up to 3 dB. At the same time, a throughput of hundreds of Mbit/s can be achieved even on low-cost FPGAs.
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DVB-RCS2 (Digital video broadcast - second generation DVB interactive satellite system) is the latest ETSI standard of the second generation for digital data transmission via satellites. The Creonic DVB-RCS2 Multi-Carrier Receiver supports multiple frequency time domain multiple access (MF-TDMA), performs all tasks of an DVB-RCS2 receiver including carriers separation, baseband conversion, demodulation, and turbo decoding. It can process intermediate frequency (IF) real signal with center IF frequencies between 0 and 100 MHz. The Creonic DBV-RCS2 Turbo Decoder is included in the receiver to provide users with Frame PDUs at the output.
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The Creonic CCSDS high performance wideband demodulator performs all tasks of an inner receiver. It allows for processing symbol rates of 500 Msymb/s on state-of-the-art FPGAs. The demodulator expects the quantized, complex baseband samples from ananalog-digital-converter (ADC) and recovers timing, frequency and phase of the complex mapped symbols. In addition, the core handles PL frame recovery and PL deframing. The output inter-face of the demodulator perfectly fits the Creonic CCSDS forward error correction IP core that implements a Serial Concatenated Convolutional Code (SCCC) decoding.
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IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic. The standard meets the need for higher data rates over backplanes and copper cables for 100 Gbit/s throughput.
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BCH codes are widely used where bit errors are scattered randomly within the codeword. The Creonic ultra-fast BCH Decoder is capable of processing an entire BCH codeword per clock cycle in a pipelined way. Therefore, it achieves outstanding data rates. The design can be parameterized at design-time to support different codeword sizes and code rates. Latency can be adjusted by insertion or removal of pipeline register stages.
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DVB-S2 (Digital video broadcast - satellite 2nd generation) is an ETSI standard of the second generation for digital data transmission via satellites. It was published in 2005, being the first standard of the second generation DVB standards (DVB-S2/-T2/-C2). Because of its capacity-approaching forward error correction, today DVB-S2 is the de-facto standard in satellite communication and other applications.
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The CCSDS 231.0 LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rate 1/2, coded block lengths 128 and 512 are specially designed for telecommand applications, but the excellent error correction performance makes it an ideal fit for further applications with highest demands on forward error correction. Applications: Telecommand communication free space optical (FSO) communication. Further applications with the highest demands on forward error correction. Standard features supported by the core support for code rate 1/2 uncoded block length of 64 and 256 bits, compliant with "TC synchronization and channel coding, recommended standard, CCSDS 231.0-B-3, Blue Book, September 2017" Your Benefits: Gains of up to 3 dB compared to viterbi decoders. Low-power and low-complexity design. Layered LDPC decoder architecture, for convergence behavior that is twice as fast as non-layered LDPC decoders. Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy. Optional fixed number of iterations for fixed latency of blocks with the same code rate and block length. Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance. Collection of statistic information (number of iterations, decoding success, number of modified bits)Available for ASIC and FPGAs (Intel® and others).Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model.
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NCR (Network Clock Reference) is a procedure to provide the master clock (i.e. time information) of the satellite to all its user terminals. Typically, NCR packets are provided periodically over a continuous DVB-S2 or DVB-S2X link. The receiving user terminal uses the knowledge of the master clock in the system to determine when it is allowed to transmit data in a time-division multiple access (TDMA) system, such as DVB-RCS or DVB-RCS2.In these TDMA systems, the same frequency band is shared among many terminals, making it mandatory to apply a strict transmission schedule for all terminals. The NCR Processor IP core has two main functionalities: NCR tracker NCR local clock ,The NCR tracker provides a local NCR clock which is frequency- and phase-latched to an incoming DVB-S2/DVB-S2X stream containing NCR information. The absolute phase difference between the NCR tracker and the clock source, e.g., satellite, depends upon the distance to the clock source. The NCR local clock provides a precisely settable NCR source clock provided a local and stable 27 MHz clock and a precise 1 PPS (Pulse Per Second) source are available.
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The DVB-GSE encapsulator and decapsulator IP cores close the gap between network protocols like Ethernet and the physical layer of the DVB family of standards. The DVB-GSE encapsulator performs the encapsulation of the network layer packets, also referred to as Protocol Data Units (PDUs), into one or more GSE packets, adding control information and performing integrity checks when necessary. Finally, it provides the data as baseband frames (BBFRAMEs) to the Creonic DVB-S2/DVB-S2X modulator. The Creonic DVB-GSE decapsulator performs the decapsulation of BBFRAMEs, containing one or more GSE packets. As a last step, it extracts the PDUs, i.e. the network layer packets, from the GSE packets and provides it to the user.
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IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic. The standard meets the need for higher data rates over backplanes and copper cables for 100 Gbit/s throughput.
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The Creonic CCSDS high performance modulator performs all tasks of an inner transmitter. The modulator expects SCCC (Serial Concatenated Convolutional Code) encoded frames as input and performs mapping, Physical Layer (PL) framing and modulation.
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The Optical Communications Terminal (OCT) standard was developed by the Space Development Agency (SDA) with the purpose of bringing interoperability across free space optical communication (FSO) systems where at least one endpoint is a space-based terminal. The Creonic SDA OCT V3.0 Encoder handles the construction of Over-The-Air (OTA) frames as indicated in the standard, a preamble followed by a header and payload data, with both fields being protected by cyclic redundancy check (CRC) and forward error correction (FEC). The Creonic SDA OCT V3.0 Decoder performs the synchronization of the Over-The-Air (OTA) frame and then decodes the header and payload data within the frame.