CCSDS 231.0 LDPC Encoder and Decoder
About this offer
The CCSDS 231.0 LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rate 1/2, coded block lengths 128 and 512 are specially designed for telecommand applications, but the excellent error correction performance makes it an ideal fit for further applications with highest demands on forward error correction. Applications: Telecommand communication free space optical (FSO) communication. Further applications with the highest demands on forward error correction. Standard features supported by the core support for code rate 1/2 uncoded block length of 64 and 256 bits, compliant with "TC synchronization and channel coding, recommended standard, CCSDS 231.0-B-3, Blue Book, September 2017" Your Benefits: Gains of up to 3 dB compared to viterbi decoders. Low-power and low-complexity design. Layered LDPC decoder architecture, for convergence behavior that is twice as fast as non-layered LDPC decoders. Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy. Optional fixed number of iterations for fixed latency of blocks with the same code rate and block length. Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance. Collection of statistic information (number of iterations, decoding success, number of modified bits)Available for ASIC and FPGAs (Intel® and others).Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model.
Details
Regional Coverage
Americas:
Latin America Region
North America Region
Asia, Pacific, and Japan:
Southeast Asia
Australia and New Zealand
Japan
Taiwan
Rest of Asia
Korea
South Asia
Europe, Middle East, and Africa:
Middle East, Turkey, and Africa
Central Eastern Europe
Western European Union Region
Commonwealth of Independent States
Northern European Union Region
Southern European Union Region
Central European Region
People's Republic of China:
People's Republic of China
Use Case
Environmental Monitoring
Others
Telematics
Artificial Intelligence : Video Surveillance and Analytics
Industry
Communications : Telecommunications
Defense and Space
Others
Technical Specifications
- Category:
- Software and IP Cores: FPGA Intellectual Property Cores: DSP: Error Detection and Correction
- End Customer Type:
-
Small and Medium sized Business
Enterprise
Included Intel Technology
Intel® Stratix® 10 FPGAs and SoC FPGAs
Stratix® V FPGAs
Intel Agilex® 7 FPGAs and SoC FPGAs
Stratix® IV FPGAs
Resources
CREONIC GMBH
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Creonic is an ISO 9001:2015 certified provider of ready-for-use IP cores for wired, wireless, fiber, and free-space optical communications. All relevant digital signal processing algorithms are covered, including, but not limited to, forward error correction, modulation, equalization, and demodulation. We offer the richest product portfolio in this field, covering standards like 3GPP 5G, DVB-S2X, DVB-RCS2, CCSDS, and Wifi. The products are applicable for ASIC and FPGA technologies and comply with the highest requirements with respect to quality and performance. As the richest in this field, the IP core product portfolio is used by dozens of customers worldwide in satellite modems and satellites. With Creonic’s chip designs, companies from start-ups to global corporations can realize their NewSpace goals. For more information please visit our website at www.creonic.com
Ccsds 231.0 Ldpc Encoder And Decoder
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