CCSDS SCCC Turbo Encoder + Decoder
About this offer
The recommended CCSDS 131.2-B-1 standard introduces a Serial Concatenated Convolutional Code (SCCC). Main goal of this code is to allow an efficient use of available bandwidth, by allowing to select from 27 valid configurations with a wide range of constellations, block lengths and code rates. The outstanding error correction performance of the SCCC code in combination with the high data rates makes this IP core the ideal fit for further applications where high throughput and high spectral efficiency is key for operation.
Technical Specifications
- Category:
- Software and IP Cores: FPGA Intellectual Property Cores: DSP: Error Detection and Correction
- Operating Systems:
-
OS Independent OS Independent family
OS Independent OS Independent family OS Independent
- End Customer Type:
-
Enterprise
Resources
Included Intel Technology
Intel® Arria® 10 FPGAs and SoC FPGAs
Stratix® V FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs
Stratix® IV FPGAs
Arria® V FPGAs and SoC FPGAs
Intel Agilex® 7 FPGAs and SoC FPGAs
CREONIC GMBH
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CREONIC GMBH
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Creonic is an ISO 9001:2015 certified provider of ready-for-use IP cores for wired, wireless, fiber, and free-space optical communications. All relevant digital signal processing algorithms are covered, including, but not limited to, forward error correction, modulation, equalization, and demodulation. We offer the richest product portfolio in this field, covering standards like 3GPP 5G, DVB-S2X, DVB-RCS2, CCSDS, and Wifi. The products are applicable for ASIC and FPGA technologies and comply with the highest requirements with respect to quality and performance. As the richest in this field, the IP core product portfolio is used by dozens of customers worldwide in satellite modems and satellites. With Creonic’s chip designs, companies from start-ups to global corporations can realize their NewSpace goals. For more information please visit our website at www.creonic.com
Ccsds Sccc Turbo Encoder + Decoder
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