GTS Interlaken Intel® FPGA IP Design Example User Guide

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ID 819203
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS Interlaken FPGA IP Design Example User Guide Archives 4. Document Revision History for GTS Interlaken IP Design Example User Guide
1. Quick Start Guide x
1.1. Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the GTS Interlaken IP Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Design Example Flow 2.3. Interface Signals 2.4. Register Map 2.5. Reset
1. Quick Start Guide
2. Design Example Description
3. GTS Interlaken FPGA IP Design Example User Guide Archives
4. Document Revision History for GTS Interlaken IP Design Example User Guide

1.4. Simulating the GTS Interlaken IP Design Example Testbench

Figure 6. Procedure
  1. At the command prompt, change to the testbench simulation directory. The directory path is <design_example_installation_dir>/example_design/testbench.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Your script should check that the SOP and EOP counts match after simulation is complete.
    Table 5.  Steps to Run Simulation
    Simulator Instructions
    VCS* MX In the command line, type: 
    sh run_vcsmx.sh
    QuestaSim* or Questa*-Intel® FPGA Edition
    In the command line, type: 
    vsim -do run_mentor.tcl
    If you prefer to simulate without bringing up the GUI, type: 
    vsim -c -do run_mentor.tcl
    Xcelium* In the command line, type: 
    sh run_xcelium.sh
  3. Analyze the results. A successful simulation sends and receives packets, and displays "Test PASSED".
    The testbench for the design example completes the following tasks:
    • Instantiates the GTS Interlaken Intel® FPGA IP core.
    • Prints PHY status.
    • Checks metaframe synchronization (SYNC_LOCK) and word (block) boundaries (WORD_LOCK).
    • Waits for individual lanes to be locked and aligned.
    • Starts transmitting packets.
    • Checks packet statistics:
      • CRC24 errors
      • SOPs
      • EOPs
    The following sample output illustrates a successful simulation test run: 
    ******************************************
                All individual lanes are locked
**************************************************

**************************************************

				INFO: Waiting for lanes to be aligned
	  				All of the receiver lanes are aligned and are ready to receive traffic.
***************************************************

***************************************************
				INFO: Start transmitting packets
***************************************************

***************************************************
				INFO: Stop transmitting packets
***************************************************

***************************************************
				INFO: Checking packets statistics
***************************************************

				CRC 24 errors reported: 0
				SOPs transmitted: 100
				EOPs transmitted: 100
				SOPs received: 100
				EOPs received: 100
				ECC error count: 0

***************************************************
				INFO: Test PASSED
***************************************************
    Note: The Interlaken design example simulation testbench sends 100 packets and receives 100 packets.
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