GTS Interlaken Intel® FPGA IP Design Example User Guide

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ID 819203
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS Interlaken FPGA IP Design Example User Guide Archives 4. Document Revision History for GTS Interlaken IP Design Example User Guide
1. Quick Start Guide x
1.1. Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the GTS Interlaken IP Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Design Example Flow 2.3. Interface Signals 2.4. Register Map 2.5. Reset
1. Quick Start Guide
2. Design Example Description
3. GTS Interlaken FPGA IP Design Example User Guide Archives
4. Document Revision History for GTS Interlaken IP Design Example User Guide

2.3. Interface Signals

Table 6.  Design Example Interface Signals
Port Name Direction Width (Bits) Description
pll_ref_clk Input 1 GTS Transceiver reference clock for PMA. Drives the RX CDR PLL.

The default clock frequency is 156.25MHz for the design example. You can modify this frequency to match the settings in IOPLL Intel FPGA IP and GTS Interlaken Intel FPGA IP.

rx_pin Input Number of lanes Receiver SERDES data pin.
tx_pin Output Number of lanes Transmit SERDES data pin.
rx_pin_n Input Number of lanes Receiver SERDES data pin.
tx_pin_n Output Number of lanes Transmit SERDES data pin.
usr_pb_reset_n Input 1 System reset.
mgmt_clk Input 1 System clock input. Clock frequency must be 100MHz.
tx_fc_clk 1 Output 1 Output reference clock to a downstream out of band RX block. Clocks the fc_data and fc_sync signals. You must connect the signal to a device pin.
tx_fc_data 1 Output 1

Output serial data pin to a downstream out-of-band RX block. You must connect this signal to a device pin.
tx_fc_sync 1 Output 1

Output sync control pin to a downstream out-of-band RX block. You must connect this signal to a device pin.
rx_fc_clk 1 Input 1 Input reference clock from an upstream out-of-band TX block. This signal clocks the fc_data and fc_sync signals. You must connect this signal to a device pin.
rx_fc_data 1 Input 1

Input serial data pin from an upstream out-of-band TX block. You must connect this signal to a device pin.
rx_fc_sync 1 Input 1 Input sync control pin from an upstream out-of-band TX block. You must connect this signal to a device pin.

1 In the Intel Quartus® Prime Static Timing Analysis report, this port appears as an unconstrained output port and should not affect your functionality when out-of band flow control is not required.
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