GTS Interlaken Intel® FPGA IP User Guide

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ID 819200
Date 3/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Interlaken FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers A. GTS Interlaken FPGA IP User Guide Archives 7. Document Revision History for GTS Interlaken Intel FPGA IP User Guide
1. About the GTS Interlaken FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Performance and Resource Utilization 1.5. Round-Trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL CLock for Your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel FPGA IPs x
2.1.1. Intel FPGA Evaluation Mode
4. Functional Description x
4.1. Data Path Flow 4.2. Modes of Operation 4.3. Performance 4.4. IP Reset 4.5. M20K ECC Support 4.6. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Erroes and In-Band Calendar Bits
4.2. Modes of Operation x
4.2.1. Interleaved and Packet Modes 4.2.2. Multi-Segment Mode
4.2.1. Interleaved and Packet Modes x
4.2.1.1. Transmit User Data Interface Examples 4.2.1.2. Receive User Data Interface Examples
4.2.2. Multi-Segment Mode x
4.2.2.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Interlaken Link and Miscellaneous Signals
1. About the GTS Interlaken FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
A. GTS Interlaken FPGA IP User Guide Archives
7. Document Revision History for GTS Interlaken Intel FPGA IP User Guide

5.2. Transmit User Interface Signals

Table 20.  Transmit User Interface SignalsThe input signals are synchronous to clk_tx_commom and output signals are synchronous to clk_rx_common.
Signal Name Width (Bits) I/O Direction Available In Description
itx_chan 8 Input Interlaken mode Transmit logic channel number for the first segment chunk. The IP core supports up to 256 channels. The IP core samples this value only when itx_sob is high and itx_num_valid has a non-zero value.
itx_chan1 8 Input Interlaken mode Transmit logic channel number for the second segment chunk. The IP core supports up to 256 channels. DUAL segment interface defines this signal. The IP core samples this value only when itx_sob is high and itx_num_valid has a non-zero value.
itx_num_valid Variable Input Interlaken mode

Indicates the number of valid 64-bit words in the current packet in the current data symbol. The width of the itx_num_valid depends on the parameter external_words and the number of segments.

If number of segments is 1, segment chunk is 1 else if number of segments is more than one, then segment_chunk is 2.

  • If external_words=4, then width=3*segment_chunk bits:[5:3,2:0].
  • If external_words=8, then width=4*segment_chunk bits: [7:4,3:0].
itx_eob 1 Input Interlaken mode Indicates the current data symbol contains the end of the burst (EOB) for the first segment chunk.

When itx_eopbits has valid value of 4’b1xxx or 4’b0001, the itx_eob is valid too, but not vice-versa.

Whenever parameter TX_PKTMOD_ONLY is set to 0, you must provide this signal. Otherwise, when parameter TX_PKTMOD_ONLY is set to 1, the IP core ignores this signal. You are responsible to comply with the BurstMax and BurstMin setting.

itx_eob1 1 Input Interlaken mode Indicates the current data symbol contains the end of the burst (EOB) for the second segment chunk.

This signal is used in DUAL segment mode only. When itx_eopbits1 has valid value of 4’b1xxx or 4’b0001, the itx_eob1 is valid too, but not vice-versa.

Whenever parameter TX_PKTMOD_ONLY is set to 0, you must provide this signal. Otherwise, when parameter TX_PKTMOD_ONLY is set to 1, the IP core ignores this signal. You are responsible to comply with the BurstMax and BurstMin setting.

itx_eopbits 4 Input Interlaken mode Number of bytes at the end of packet for the first segment chunk. Indicates whether the current data symbol contains the end of a packet (EOP) with or without an error, and specifies the number of valid bytes in the current end-of-packet, non-error 8-byte data word, if relevant.
You must set the value of itx_eopbits as following:
  • 4b’0000: No end of packet, no error.
  • 4b’0001: Error and end of packet.
  • 4b’1xxx: End of packet. xxx indicates the number of valid bytes in the final valid 8-byte word of the packet, as following:
    • 000: all 8 bytes are valid.
    • 001: 1 byte is valid.
    • ...
    • 111: 7 bytes are valid.
All other values (4'b01xx, 4'b001x) are undefined. The valid bytes always start in bit positions [63:56] of the final valid data word of the packet.
itx_eopbits1 4 Input Interlaken mode

Number of bytes at the end of packet for the second segment chunk.

This signal is only defined in the DUAL segment interface.

Indicates whether the current data symbol contains the end of a packet (EOP) with or without an error, and specifies the number of valid bytes in the current end-of-packet, non-error 8-byte data word, if relevant.

You must set the value of itx_eopbits1 as following:

• 4b’0000: no end of packet, no error.

• 4b’0001: Error and end of packet.

• 4b’1xxx: End of packet.

xxx indicates the number of valid bytes in the final valid 8-byte word of the packet, as following:

— 000: all 8 bytes are valid.

— 001: 1 byte is valid.

— ...

— 111: 7 bytes are valid.

All other values (4'b01xx, 4'b001x) are undefined. The valid bytes always start in bit positions [63:56] of the final valid data word of the packet.

itx_sob Variable Input Interlaken mode

Indicates the current data symbol contains the start of a burst (SOB). If the IP core is in Interleaved mode, you are responsible for providing this start of the burst signal. If the IP core is in Packet mode, the IP core ignores this signal.

The IP core samples the itx_chan signal during this cycle.

  • [0] - single segment with number of words = 4
  • [1] - single segment with number of words = 8
  • [1:0] - Dual segment

The segment order is defined as {, segment1, segment0} with segment 1 at MSB.

Using two segment as an example. This signal has the following valid values:

[1] : indicates SOB for the first segment(segment 1).

[0]: indicate SOB for the second segment(segment 0).

For example:

If number of words=8, Number of segments=2, tx_num_valid [7:4] = 4, tx_num_valid [4:0]=4. The second segment will start at word [3], sob [1:0]=11 (binary).

If number of words=8, Number of segments=2, tx_num_valid [7:4] = 1, tx_num_valid [4:0]=1. The second segment will still start at word [3], sob [1:0]=11 (binary).

itx_sop Variable Input Interlaken mode

Indicates the current data symbol on itx_din_words contains the start of a packet (SOP).

  • [0] - single segment with number of words = 4
  • [1] - single segment with number of words = 8
  • [1:0] - Dual segment

The segment order is defined as {segment1, segment0} with segment 1 at MSB.

Using two segment as an example. This signal has the following valid values:

[1] : indicates SOP for the first segment(segment 1)

[0]: indicate SOP for the second segment(segment 0).

For example:

If number of words = 8, Number of segments=2, tx_num_valid [7:4] = 4, tx_num_valid [4:0]=4. The second segment will start at word [3], sop [1:0]=11 (binary).

If number of words = 8, Number of segments=2, tx_num_valid [7:4] = 1, tx_num_valid [4:0]=1. The second segment will still start at word[3], sop[1:0]=11 (binary).

itx_din_words Variable Input Interlaken mode The 64-bit words of transmit data (one data symbol). The width of the itx_din_words depends on the parameter external_words.
  • If external_words=4, then width=256 bits.
  • If external_words=8, then width=512 bits.

The first and last data word is in [511:448] and [63:0] respectively.
itx_calendar N Input Interlaken mode Multiple pages (16 bits per page) of calendar input bits. The IP core copies these bits to the in-band flow control bits in N control words that it sends on the Interlaken link. N is the value of the Number of calendar pages parameter, which can be any of 1, 2, 4, 8. or 16. This signal is synchronous with tx_usr_clk, although it is not part of the user data transfer protocol.
itx_ready 1 Output Interlaken mode Flow control signal to back pressure transmit traffic. When this signal is high, you can send traffic to the IP core. When this signal is low, you should stop sending traffic to the IP core within one to four cycles. You should provide itx_num_valid only after itx_ready is asserted.
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