GTS Interlaken Intel® FPGA IP User Guide

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ID 819200
Date 3/31/2024
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Document Table of Contents
Document Table of Contents x
1. About the GTS Interlaken FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers A. GTS Interlaken FPGA IP User Guide Archives 7. Document Revision History for GTS Interlaken Intel FPGA IP User Guide
1. About the GTS Interlaken FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Performance and Resource Utilization 1.5. Round-Trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL CLock for Your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel FPGA IPs x
2.1.1. Intel FPGA Evaluation Mode
4. Functional Description x
4.1. Data Path Flow 4.2. Modes of Operation 4.3. Performance 4.4. IP Reset 4.5. M20K ECC Support 4.6. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Erroes and In-Band Calendar Bits
4.2. Modes of Operation x
4.2.1. Interleaved and Packet Modes 4.2.2. Multi-Segment Mode
4.2.1. Interleaved and Packet Modes x
4.2.1.1. Transmit User Data Interface Examples 4.2.1.2. Receive User Data Interface Examples
4.2.2. Multi-Segment Mode x
4.2.2.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Interlaken Link and Miscellaneous Signals
1. About the GTS Interlaken FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
A. GTS Interlaken FPGA IP User Guide Archives
7. Document Revision History for GTS Interlaken Intel FPGA IP User Guide

4.4. IP Reset

The Interlaken IP core variations have a single asynchronous reset, the reset_n signal. The Interlaken IP core manages the initialization sequence internally. After you de-assert reset_n (raise it after asserting it low), the IP core automatically goes through the entire reset sequence.

The reset_n signal only reset the IP core, while the tx_rst_n and rx_rst_n signals reset the soft reset controller in Direct-PHY IP.

The tx_rst_ack_n and rx_rst_ack_n are active low asynchronous reset acknowledge signals from Direct-PHY IP which indicate that the soft reset controller has successfully entered reset mode and you can now release the reset_n, tx_rst_n, and rx_rst_n signals. The tx_rst_ack_n and rx_rst_ack_n signals stay low until you release the tx_rst_n, and rx_rst_n signals respectively.
Figure 15. Reset Timing Diagram

Following completion of the reset sequence internally, the Interlaken IP core begins link initialization. If your IP core and its Interlaken link partner initialize the link successfully, you can observe the assertion of the lane and link status signals according to the Interlaken specification. For example, you can monitor the tx_lanes_aligned, sync_locked, word_locked, and rx_lanes_aligned output status signals.

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