GTS Interlaken Intel® FPGA IP User Guide

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ID 819200
Date 3/31/2024
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Document Table of Contents
Document Table of Contents x
1. About the GTS Interlaken FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers A. GTS Interlaken FPGA IP User Guide Archives 7. Document Revision History for GTS Interlaken Intel FPGA IP User Guide
1. About the GTS Interlaken FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Performance and Resource Utilization 1.5. Round-Trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL CLock for Your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel FPGA IPs x
2.1.1. Intel FPGA Evaluation Mode
4. Functional Description x
4.1. Data Path Flow 4.2. Modes of Operation 4.3. Performance 4.4. IP Reset 4.5. M20K ECC Support 4.6. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Erroes and In-Band Calendar Bits
4.2. Modes of Operation x
4.2.1. Interleaved and Packet Modes 4.2.2. Multi-Segment Mode
4.2.1. Interleaved and Packet Modes x
4.2.1.1. Transmit User Data Interface Examples 4.2.1.2. Receive User Data Interface Examples
4.2.2. Multi-Segment Mode x
4.2.2.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Interlaken Link and Miscellaneous Signals
1. About the GTS Interlaken FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
A. GTS Interlaken FPGA IP User Guide Archives
7. Document Revision History for GTS Interlaken Intel FPGA IP User Guide

1.1. Features

The GTS Interlaken Intel® FPGA IP core supports the following features:
  • General features:
    • Compliant with the Interlaken Protocol Specification, Revision 1.2.
    • Compliant with the Interlaken Reed-Solomon Forward Error Correction (RS-FEC) Extension Specification, Revision 1.1.
    • Supports 4, 6, and 8 serial lanes in configurations that provide up to 206.25 Gbps raw bandwidth. Refer to the Table: IP Supported Combinations of Number of Lanes and Data Rates below for more details on current list of supported configurations.
    • Supports per-lane data rates of 6.25, 12.5 and 25.78125 Gbps using the Intel FPGA on-chip high-speed transceivers.
  • User interface features:
    • Supports dynamically configurable BurstMax and BurstMin values.
    • Supports Packet mode and Interleaved mode for user data transfer.
    • Supports up to 256 logical channels in out-of-the-box configuration.
    • Supports multi-segment user interface.
  • Flow-control features:
    • Supports optional out-of-band flow control blocks.
    • Supports optional user-controlled in-band flow control with 1, 2, 4, 8, or 16 16-bit calendar pages.
    • Supports error correction code (ECC) for memory block implementation with the IP.
  • Line-side features:
    • Supports per lane data rates of 6.25, 12.5, and 25.78125 Gbps using non-return-to-zero (NRZ) mode.
Table 1.  IP Supported Combinations of Number of Lanes and Data RatesThe following combinations are supported in the Quartus® Prime Pro Edition software version 24.1.
Number of Lanes Lane Rate (Gbps)
6.25 10.3125 12.5
4 Yes - Yes
6 - - -
8 - - Yes
Table 2.  IP Theoretical Raw Aggregate BandwidthThe following combinations are supported in the Quartus® Prime Pro Edition software version 24.1
PMA Type Lane Rate (Gbps) Number of Lanes User Interface Width (words) Data Width (bits) Raw Aggregate Bandwidth (Gbps)
FGT 6.25 4 4 256 25
12.5 4 4 256 50
8 8 512 100
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