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1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
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3.5. Generate GTS EHIP Design Example
To generate a design example for your IP variant, follow these steps:
Figure 7. Procedure
- On the IP tab, specify the parameters for your IP core variation. For the specific IP parameter settings, refer to Selected IP Parameter Settings table in simulation, compilation, and validation sections.
- Specify the parameters in the Example Design tab as shown in the image.
Figure 8. Design Example TabBy default Enable fast simulation parameter is enabled for AN/LT design under Simulations Options tab. In your design example testbench, you can utilize the Fast Sim model to reduce the IP simulation time.
Table 14. Design Example Parameters Parameters Value Default Description Auto-Negotiation and Link Training Options Tab Enable auto-negotiation and link training - Enable
- Disable
Disable When selected, the IP includes additional soft logic to perform Auto-Negotiation and Link Training (AN/LT). Available Example Designs Select Design - Single Instance of IP Core
- Multi Instance of IP Core
- None
Single Instance of IP Core
Selects the number of instance of IP core for example design. Example Design Files - Simulation
- Synthesis
- Simulation
- Synthesis
Simulation option generates the testbench and compilation-only project. Synthesis option generates the hardware design example.
Generated HDL Format Tab Generated File Format - Verilog
- VHDL
Verilog
Select the HDL files format. If you select VHDL, you must simulate the testbench with a mixed-language simulator. Target Development Kit Tab Board - Agilex™ 5 FPGA E-Series 065B Premium Development Kit (ES1)
- None
None
Target development kit option specifies the target development kit used to generate the project. Ensure the selected device is your targeted device and adjust the pin assignments in the .qsf file. OPN: A5ED065BB32AE6SR0
Select Device Initialization Clock - OSC_CLK_1_25MHZ
- OSC_CLK_1_100MHZ
- OSC_CLK_1_125MHZ
OSC_CLK_1_125MHZ Selects the Device Initialization Clock. Enable Signal Tap Option - Enable
- Disable
Disable Enable the option to include debug signals (Refer to Debug Signals) into the Signal Tap file in the generated design example. - Click the Generate Example Design button.
- Once the design example is generated, click the Launch Example Design in Quartus.
The software generates all design files in sub-directories. You require these files to run simulation and compilation. For information on simulation, compilation, and validation of each variant, refer to the desired chapter.
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