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Ixiasoft
Visible to Intel only — GUID: iia1715808686502
Ixiasoft
9. Simulate, Compile, and Validate - Multiple Instance
The multiple IP core design example demonstrates three instantiations of the GTS Ethernet Intel® FPGA Hard IP with each instance supporting 10GE/25GE Ethernet rates.
Selected IP Parameter Settings | Value |
---|---|
IP Tab: General Options | |
Ethernet Operation Mode | Ethernet General |
Client interface | MAC Avalon® ST |
MAC Use case | 1 Port MAC |
PMA reference frequency | 156.25 MHz |
System PLL frequency | 322.265625 MHz |
Enable dedicated CDR clock output | Uncheck |
Base_profile -> Port #0 IP Configuration | |
Ethernet Mode | 10G-1 |
FEC mode | None |
Example Design Tab: Available Example Designs | |
Select Design | Multi instance of IP core |
For more information about steps of how to generate a design example, refer to the Generate GTS EHIP Design Example.
Section Content
Design Example Features
Design Example Components
Simulate the Design Example
Compile the Design Example
Validate the Design Example