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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. PCS Direct Signals: IEEE
3.4.6. PCS Direct Signals: IEEE_FLEXE_66/PCS66
3.4.7. Custom Cadence Control and Status Signals
3.4.8. RX PMA Status Signals
3.4.9. TX and RX PMA and Core Interface FIFO Signals
3.4.10. Avalon Memory-Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
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3.13.2. GTS Attribute Access Method
Using the GTS attribute access method, you update the GTS PMA registers to configure hardware with a specific sequence of commands.
For example, you can configure serial internal loopback, TX and RX polarity inversion using the GTS attribute access method. The GTS attribute access method consists of 4 steps in a sequence as shown below:
You can create a function to write data, or read to and from GTS attribute access addresses. The data is comprised of data field[31:16], option field[15:12], lane number field[11:8], and opcode field[7:0]. The following examples use the tcl process as shown below:
- Write a data value to the LINK_MNG_SIDE_CPI_REGS register to assert a service request.
- Read the PHY_SIDE_CPI_REGS register to confirm the request has been acknowledged and completed; if not, repeat this step.
- Write a data value to the LINK_MNG_SIDE_CPI_REGS register to deassert the service request.
- Read the PHY_SIDE_CPI_REGS register to confirm the request in step 3 has been acknowledged; if not, repeat this step.
Channels | LINK_MNG_SIDE_CPI_REGS Address | PHY_SIDE_CPI_REGS Address |
---|---|---|
Channel 0 | 0x000A403C | 0x000A4040 |
Channel 1 | 0x001A403C | 0x001A4040 |
Channel 2 | 0x002A403C | 0x002A4040 |
Channel 3 | 0x003A403C | 0x003A4040 |
Channel 4 | 0x004A403C | 0x004A4040 |
Channel 5 | 0x005A403C | 0x005A4040 |
Channel 6 | 0x006A403C | 0x006A4040 |
Channel 7 | 0x007A403C | 0x007A4040 |
Loopback Mode | Polarity Setup | |
---|---|---|
Data field[31:16] | Enable serial loopback: 0x6 Enable TX to RX parallel loopback: 0x4 Disable loopback: 0x0 |
Reverse: 0x1 Revert back: 0x0 |
Option field [15:12] | Bit [15] SERVICE_REQ to indicate a request: 0 = no request, 1 = service requested. Bit [14] RESET: 0 = not in reset, 1 = in reset. Bit [13] SET_GET: 0 = GET parameters, 1 = SET parameters. Bit [12]: reserved |
|
Lane number field[11:8] | Use 0xA5000[1:0], 0x1A5000[1:0]… 0x7A5000[1:0] to read back logical lane 0, 1 until lane 7’s physical lane number.
|
|
Opcode field[7:0] | 0x40 | TX polarity: 0x65 RX polarity: 0x66 |
proc attribute_access {{data field} {option field} {lane number field} {opcode field}}You can use any programming language to perform the read and writes. For the other GTS PMA lanes, refer to GTS Attribute Access Addresses for JTAG Master that Controls 8 channels for LINK_MNG_SIDE_CPI_REGS and PHY_SIDE_CPI_REGS, and refer to GTS Attribute Access Data Value 1 for lane number field information.